index 9853337a7045f298627347099d43400a548e5c57..5296f3f24ccb4a6d83ef3bad901b06e610d9264c 100644 (file)
* @brief
* Device DDR controller definitions
*/
-#define DEVICE_DDR_BASE 0x80000000
+#define DEVICE_DDR_BASE 0x78000000
#define targetEmifType() ibl_EMIF_TYPE_31
/**
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
+#define ECC_BLOCK_SIZE 256
+
+/* NAND address pack macro */
+#define PACK_ADDR(col, page, block) \
+ ((col & 0x00000fff) | ((page & 0x0000003f)<<16) | ((block & 0x000003ff) << 22 ))
/**
* @brief
*/
#define deviceReadBootDevice() BOOT_DEVICE_I2C
-#define IBL_REENTER_ROM 0
-#define iblReEnterRom()
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+