Modified IBL to re-init PLL in DDR controller, added UART
[keystone-rtos/ibl.git] / src / device / c64x / make / makefile
index b5fbbc0f61f73643dd196b075d45f3cce939519e..d1af17ad938f5dda31ba7f50691c770018f31979 100644 (file)
@@ -101,6 +101,7 @@ C6X_C_DIR+= ;$(IBL_ROOT)/hw/nands
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/nors
 C6X_C_DIR+= ;$(IBL_ROOT)/driver/eth
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/spi
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/uart/c66x_uart
 export C6X_C_DIR
 
 vpath % $(IBL_ROOT)/device/$(TARGET)