diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
index e7a2cf7ec894cd4066d0632de80e3d0dd7513cbf..ba72d9045a489fc06cc7647e70f5c969510da839 100755 (executable)
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
#include "spi_api.h"
#include <string.h>
#include <stdint.h>
+#include "target.h"
#include "uart.h"
#define PLL_DDR_INIT_LOOPMAX 10
#define IBL_RESULT_CODE_LOC 17
extern cregister unsigned int DNUM;
-#define DDR3_TEST_ENABLE
-
-#ifdef DDR3_TEST_ENABLE
-/**
- * @brief Simple DDR3 test
- *
- * @details
- * This function performs a simple DDR3 test for a memory range
- * specified below and returns -1 for failure and 0 for success.
- */
-
-#define DDR3_TEST_START_ADDRESS 0x80000000
-
-#define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
-
-static int32_t ddr3_memory_test (void)
-{
- uint32_t index, value;
-
- /* Write a pattern */
- for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
- *(volatile uint32_t *) index = (uint32_t)index;
- }
-
- /* Read and check the pattern */
- for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-
- value = *(uint32_t *) index;
-
- if (value != index) {
- return -1;
- }
- }
-
- /* Write a pattern for complementary values */
- for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
- *(volatile uint32_t *) index = (uint32_t)~index;
- }
-
- /* Read and check the pattern */
- for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-
- value = *(uint32_t *) index;
-
- if (value != ~index) {
- return -1;
- }
- }
-
- return 0;
-}
-
-#endif
/**
* @brief Determine if an address is local
DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xff; /* replacement addr + perm*/
DEVICE_REG_XMPAX_H(2) = 0x2100000B; /* base addr + seg size (64KB)*/
+ if (ibl.ddrConfig.configDdr != 0)
+ hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+
+#ifdef PLL_REINIT_WORKAROUND
for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
{
- if(loopcount !=0) /*Do not call PLL sequence for the first time */
- {
/* Calling MAIN, PA, DDR PLL init */
- if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
- hwPllSetPll (MAIN_PLL,
- ibl.pllConfig[ibl_MAIN_PLL].prediv,
- ibl.pllConfig[ibl_MAIN_PLL].mult,
- ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+ if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv,
+ ibl.pllConfig[ibl_MAIN_PLL].mult,
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv);
- if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
- hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
- ibl.pllConfig[ibl_NET_PLL].prediv,
- ibl.pllConfig[ibl_NET_PLL].mult,
- ibl.pllConfig[ibl_NET_PLL].postdiv,
- ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
- ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+ if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+ hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+ ibl.pllConfig[ibl_NET_PLL].prediv,
+ ibl.pllConfig[ibl_NET_PLL].mult,
+ ibl.pllConfig[ibl_NET_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
- if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
- hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
- ibl.pllConfig[ibl_DDR_PLL].prediv,
- ibl.pllConfig[ibl_DDR_PLL].mult,
- ibl.pllConfig[ibl_DDR_PLL].postdiv,
- ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
- ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
- }
+ if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+ hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+ ibl.pllConfig[ibl_DDR_PLL].prediv,
+ ibl.pllConfig[ibl_DDR_PLL].mult,
+ ibl.pllConfig[ibl_DDR_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
if (ibl.ddrConfig.configDdr != 0)
hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
- /* Init UART */
- uart_init();
-#ifdef DDR3_TEST_ENABLE
- if (ddr3_memory_test() == 0)
- {
- break;
- }
-#endif
-
+
+ if (ddr3_memory_test() == 0)
+ {
+ break;
+ }
}
+ /* Init UART again because we are re-initializing the PLL's */
+ uart_init();
+
if (loopcount < 10)
{
ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + '0';
uart_write_string("IBL: PLL and DDR Initialization Complete",0);
}
uart_write_string(ddr_result_code_str,0);
-
+#endif
}