index 853a4a073373d1063f2f59235036d9952af03f60..763207ff7dc019f01b63a66cc3d0fb9e2f3d5bdf 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
#ifndef _TARGET_H
#define _TARGET_H
#include "types.h"
-
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
/**
* @brief
#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
#define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
+#define ECC_BLOCK_SIZE 256
+
+/* NAND address pack macro */
+#define PACK_ADDR(col, page, block) \
+ ((col & 0x000000ff) | ((page & 0x0000001f) << 9) | ((block & 0x00000fff) << 14))
/**
* @brief
*/
#define IBL_ENABLE_PCIE_WORKAROUND 1
+/**
+ * @brief
+ * DDR start and end address needed for DDR memory test
+ */
+#define DDR3_TEST_START_ADDRESS 0x80000000
+#define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
+
+/**
+ * @brief
+ * Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
+ */
+#define PLL_REINIT_WORKAROUND
+
+extern int32_t ddr3_memory_test();
+
#endif /* _TARGET_H */