index 32e60bda94865f1ebe56e60b3484efa58eaa60fd..1e6a18dad35597974ed167c6f41e36d83ba61ae6 100755 (executable)
thereby, 3ms=3000us=4201680 */
ddr3_wait(4201680); //Wait 3ms for leveling to complete
}
+ else if (v == DEVICE_C6657_JTAG_ID_VAL)
+ {
+ KICK0 = KICK0_UNLOCK;
+ KICK1 = KICK1_UNLOCK;
+
+ /**************** 3.3 Leveling register configuration ********************/
+ DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
+ DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
+ DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
+ DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
+ DDR3_CONFIG_REG_23 |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
+
+ /**************** 3.3 Partial Automatic Leveling ********************/
+ DATA0_WRLVL_INIT_RATIO = 0x00;
+ DATA1_WRLVL_INIT_RATIO = 0x00;
+ DATA2_WRLVL_INIT_RATIO = 0x00;
+ DATA3_WRLVL_INIT_RATIO = 0x00;
+ DATA4_WRLVL_INIT_RATIO = 0x33;
+ DATA5_WRLVL_INIT_RATIO = 0x3A;
+ DATA6_WRLVL_INIT_RATIO = 0x2C;
+ DATA7_WRLVL_INIT_RATIO = 0x2C;
+ DATA8_WRLVL_INIT_RATIO = 0x1C;
+
+ DATA0_GTLVL_INIT_RATIO = 0x00;
+ DATA1_GTLVL_INIT_RATIO = 0x00;
+ DATA2_GTLVL_INIT_RATIO = 0x00;
+ DATA3_GTLVL_INIT_RATIO = 0x00;
+ DATA4_GTLVL_INIT_RATIO = 0xB7;
+ DATA5_GTLVL_INIT_RATIO = 0xB1;
+ DATA6_GTLVL_INIT_RATIO = 0xA4;
+ DATA7_GTLVL_INIT_RATIO = 0xA4;
+ DATA8_GTLVL_INIT_RATIO = 0x98;
+
+ //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
+ DDR_DDRPHYC &= ~(0x00008000);
+ DDR_DDRPHYC |= (0x00008000);
+ DDR_DDRPHYC &= ~(0x00008000);
+
+ /***************** 3.4 Basic Controller and DRAM configuration ************/
+ DDR_SDRFC = 0x0000515C; // enable configuration
+
+ /* DDR_SDTIM1 = 0x1113783C; */
+ TEMP = 0;
+ TEMP |= 0x9 << 25; // T_RP bit field 28:25
+ TEMP |= 0x9 << 21; // T_RCD bit field 24:21
+ TEMP |= 0x9 << 17; // T_WR bit field 20:17
+ TEMP |= 0x17 << 12; // T_RAS bit field 16:12
+ TEMP |= 0x20 << 6; // T_RC bit field 11:6
+ TEMP |= 0x1 << 3; // T_RRD bit field 5:3
+ TEMP |= 0x4; // T_WTR bit field 2:0
+ DDR_SDTIM1 = TEMP;
+
+ /* DDR_SDTIM2 = 0x304F7FE3; */
+ TEMP = 0;
+ TEMP |= 0x3 << 28; // T_XP bit field 30:28
+ TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
+ TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
+ TEMP |= 0x4 << 3; // T_RTP bit field 5:3
+ TEMP |= 0x3; // T_CKE bit field 2:0
+ DDR_SDTIM2 = TEMP;
+
+ /* DDR_SDTIM3 = 0x559F849F; */
+ TEMP = 0;
+ TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
+ TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
+ TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
+ TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
+ TEMP |= 0x6A << 4; // T_RFC bit field 12:4
+ TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
+ DDR_SDTIM3 = TEMP;
+
+ DDR_DDRPHYC = 0x0010010F;
+
+ DDR_ZQCFG = 0x70074C1F;
+
+ DDR_PMCTL = 0x0;
+
+ DDR_SDRFC = 0x0000515C; // enable configuration
+
+ /* DDR_SDCFG = 0x63062A32; */
+ /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */
+ TEMP = 0;
+ TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
+ TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
+ TEMP |= 0x2 << 24; // DDR_TERM bit field 26:24
+ TEMP |= 0x2 << 21; // DYN_ODT bit field 22:21
+ TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
+ TEMP |= 0x3 << 16; // CWL bit field 17:16
+ TEMP |= 0x1 << 14; // NM bit field 15:14
+ TEMP |= 0xE << 10; // CL bit field 13:10
+ TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7
+ TEMP |= 0x3 << 4; // IBANK bit field 6:4
+ TEMP |= 0x0 << 3; // EBANK bit field 3:3
+ TEMP |= 0x2; // PAGESIZE bit field 2:0
+ DDR_SDCFG = TEMP;
+
+ /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+ * so, 100 us = 100000 ns = 140056 cycles
+ thereby, 600us=840336 */
+ ddr3_wait(840336); //Wait 600us for HW init to complete
+
+ DDR_SDRFC = 0x0000144F; //Refresh rate = (7.8*666MHz]
+
+ /***************** 4.2.1 Partial automatic leveling ************/
+ DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable automatic leveling
+
+ /*Trigger automatic leveling - This ignores read DQS leveling result and uses ratio forced value
+ Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
+ Actual time = ~10-15 ms */
+ DDR_RDWR_LVL_CTRL = 0x80000000;
+
+ /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+ * so, 100 us = 100000 ns = 140056 cycles
+ thereby, 3ms=3000us=4201680 */
+ ddr3_wait(4201680); //Wait 3ms for leveling to complete
+
+ }
else
{
/* C64x configuration */