DDR config updates for Shannon PG 2.0

[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c

diff --git a/src/hw/ddrs/emif4/emif4.c b/src/hw/ddrs/emif4/emif4.c
index 2ef2a2ba61801c14eea3de72733c769e26c172da..32e60bda94865f1ebe56e60b3484efa58eaa60fd 100755 (executable)
--- a/src/hw/ddrs/emif4/emif4.c
+++ b/src/hw/ddrs/emif4/emif4.c
@@ -19,6 +19,9 @@
 #define KICK0_UNLOCK           0x83e70b13
 #define KICK1_UNLOCK           0x95a4f1e0
 
+#define DDR3PLLCTL0            *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
+#define DDR3PLLCTL1            *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0334)
+
 // DDR3 definitions
 #define DDR_BASE_ADDR 0x21000000
 
@@ -67,7 +70,6 @@
 
 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
-#define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
 
@@ -81,7 +83,7 @@ static void ddr3_wait (uint32 del)
 {
     volatile unsigned int i;
 
-    for (i = 0; i < del; i++);
+    for (i = 0; i < del; i++) asm (" nop ");
 
 }
 
@@ -104,19 +106,15 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
 
        KICK0 = KICK0_UNLOCK;
        KICK1 = KICK1_UNLOCK;
-
         
        /**************** 3.3 Leveling register configuration ********************/
         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
-        /* Set for Partial Automatic Levelling, QTT */
-        DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
+        DDR3_CONFIG_REG_23 |= 0x00000200;    // See section 4.2.1, set for partial automatic levelling
             
-       //Values with invertclkout = 1
       /**************** 3.3 Partial Automatic Leveling ********************/
-      /* Is this required for C6670 also? QTT */          
       DATA0_WRLVL_INIT_RATIO = 0x5E;
       DATA1_WRLVL_INIT_RATIO = 0x5E;
       DATA2_WRLVL_INIT_RATIO = 0x5E;
@@ -156,22 +154,22 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
        TEMP |= 0x4; // T_WTR bit field 2:0
        DDR_SDTIM1 = TEMP;
 
-      /* DDR_SDTIM2   = 0x304F7FE3; */
+      /* DDR_SDTIM2   = 0x30717FE3; */
        TEMP = 0;
        TEMP |= 0x3 << 28; // T_XP bit field 30:28
-       TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
+       TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
        TEMP |= 0x3; // T_CKE bit field 2:0
        DDR_SDTIM2 = TEMP;
 
-      /*  DDR_SDTIM3   = 0x559F849F; */
+      /*  DDR_SDTIM3   = 0x559F86AF; */
        TEMP = 0;
        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
-       TEMP |= 0x49 << 4; // T_RFC bit field 12:4
+       TEMP |= 0x6a << 4; // T_RFC bit field 12:4
        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
        DDR_SDTIM3 = TEMP; 
 
@@ -200,25 +198,25 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
          TEMP |= 0x2; // PAGESIZE bit field 2:0
          DDR_SDCFG = TEMP;
 
-       for (i = 0; i < 12000; i++) {
-               ddr3_wait(1000);             //Wait 600us for HW init to complete
-       }
+       /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+       * so, 100 us = 100000 ns = 140056 cycles
+          thereby, 600us=840336 */
+         ddr3_wait(840336);             //Wait 600us for HW init to complete
 
         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
 
-        /* 4.2.1 Partial automatic levelling because we set DDR3_CONFIG_REG_23 above? */
-        /* QTT : Isnt this partial automatic levelling?*/
-        DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
+      /***************** 4.2.1 Partial automatic leveling ************/
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable automatic leveling
    
-        /* QTT : Isnt this partial automatic levelling?*/
-        /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
+        /*Trigger automatic leveling - This ignores read DQS leveling result and uses ratio forced value
           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
           Actual time = ~10-15 ms */
         DDR_RDWR_LVL_CTRL = 0x80000000; 
 
-       for (i = 0; i < 30000; i++) {
-               ddr3_wait(1000); //Wait 3ms for leveling to complete
-       }
+       /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+       * so, 100 us = 100000 ns = 140056 cycles
+          thereby, 3ms=3000us=4201680 */
+       ddr3_wait(4201680); //Wait 3ms for leveling to complete
     }
     else
     {