#define KICK1_UNLOCK 0x95a4f1e0
#define DDR3PLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
-#define DDR3PLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
+#define DDR3PLLCTL1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0334)
// DDR3 definitions
#define DDR_BASE_ADDR 0x21000000
#define DDR3_CONFIG_REG_0 (*(volatile unsigned int*)(0x02620404))
#define DDR3_CONFIG_REG_12 (*(volatile unsigned int*)(0x02620434))
-#define DDR3_CONFIG_REG_13 (*(volatile unsigned int*)(0x02620460))
#define DDR3_CONFIG_REG_23 (*(volatile unsigned int*)(0x02620460))
#define DDR3_CONFIG_REG_24 (*(volatile unsigned int*)(0x02620464))
{
volatile unsigned int i;
- for (i = 0; i < del; i++);
+ for (i = 0; i < del; i++) asm (" nop ");
}
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
-
- /* 1333 MHz data rate */
- /***************** 2.2 DDR3 PLL Configuration ************/
- DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
- DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
- DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ
-
- for (i = 0;i < 20;i++)
- ddr3_wait(1000); //Wait for reset to complete
-
- DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit
-
- for (i = 0;i < 500;i++)
- ddr3_wait(1000); //Wait for PLL lock
-
-
- /**************** 3.0 Leveling Register Configuration ********************/
- /* Using partial automatic leveling due to errata */
- /**************** 3.2 Invert Clock Out ********************/
+ /**************** 3.3 Leveling register configuration ********************/
DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
- DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
+ DDR3_CONFIG_REG_23 |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
- //Values with invertclkout = 1
- /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+ /**************** 3.3 Partial Automatic Leveling ********************/
DATA0_WRLVL_INIT_RATIO = 0x5E;
DATA1_WRLVL_INIT_RATIO = 0x5E;
DATA2_WRLVL_INIT_RATIO = 0x5E;
DDR_DDRPHYC |= (0x00008000);
DDR_DDRPHYC &= ~(0x00008000);
- /***************** 2.3 Basic Controller and DRAM configuration ************/
+ /***************** 3.4 Basic Controller and DRAM configuration ************/
DDR_SDRFC = 0x00005162; // enable configuration
/* DDR_SDTIM1 = 0x1113783C; */
TEMP |= 0x4; // T_WTR bit field 2:0
DDR_SDTIM1 = TEMP;
- /* DDR_SDTIM2 = 0x304F7FE3; */
+ /* DDR_SDTIM2 = 0x30717FE3; */
TEMP = 0;
TEMP |= 0x3 << 28; // T_XP bit field 30:28
- TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
+ TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
TEMP |= 0x4 << 3; // T_RTP bit field 5:3
TEMP |= 0x3; // T_CKE bit field 2:0
DDR_SDTIM2 = TEMP;
- /* DDR_SDTIM3 = 0x559F849F; */
+ /* DDR_SDTIM3 = 0x559F86AF; */
TEMP = 0;
TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
- TEMP |= 0x49 << 4; // T_RFC bit field 12:4
+ TEMP |= 0x6a << 4; // T_RFC bit field 12:4
TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
DDR_SDTIM3 = TEMP;
TEMP |= 0x2; // PAGESIZE bit field 2:0
DDR_SDCFG = TEMP;
- for (i = 0; i < 12000; i++) {
- ddr3_wait(1000); //Wait 600us for HW init to complete
- }
+ /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+ * so, 100 us = 100000 ns = 140056 cycles
+ thereby, 600us=840336 */
+ ddr3_wait(840336); //Wait 600us for HW init to complete
DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz]
- DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
+ /***************** 4.2.1 Partial automatic leveling ************/
+ DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable automatic leveling
- /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
+ /*Trigger automatic leveling - This ignores read DQS leveling result and uses ratio forced value
Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
Actual time = ~10-15 ms */
DDR_RDWR_LVL_CTRL = 0x80000000;
- for (i = 0; i < 30000; i++) {
- ddr3_wait(1000); //Wait 3ms for leveling to complete
- }
+ /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
+ * so, 100 us = 100000 ns = 140056 cycles
+ thereby, 3ms=3000us=4201680 */
+ ddr3_wait(4201680); //Wait 3ms for leveling to complete
}
else
{