index 39c1904fd8f323558237a550ec78faa5db1596c2..a7f94ddd87ad66f498fa3140724496af45842c11 100644 (file)
#define DDR_RDWR_LVL_RMP_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
#define DDR_RDWR_LVL_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
#define DDR_DDRPHYC (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
+#define DDR_ZQCFG (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
#define DATA0_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262043C))
#define DATA1_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620440))
#define DATA7_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620458))
#define DATA8_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262045C))
+#define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262040C))
+#define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620410))
+#define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620414))
+#define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620418))
+#define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262041C))
+#define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620420))
+#define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620424))
+#define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620428))
+#define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262042C))
+
#define RDWR_INIT_RATIO_0 (*(volatile unsigned int*)(0x0262040C))
#define RDWR_INIT_RATIO_1 (*(volatile unsigned int*)(0x02620410))
#define RDWR_INIT_RATIO_2 (*(volatile unsigned int*)(0x02620414))
#define RDWR_INIT_RATIO_7 (*(volatile unsigned int*)(0x02620428))
#define RDWR_INIT_RATIO_8 (*(volatile unsigned int*)(0x0262042C))
+
#define DDR3_CONFIG_REG_0 (*(volatile unsigned int*)(0x02620404))
#define DDR3_CONFIG_REG_12 (*(volatile unsigned int*)(0x02620434))
#define DDR3_CONFIG_REG_13 (*(volatile unsigned int*)(0x02620460))
#define WR_DATA_SLAVE_RATIO 0xE9
#define FIFO_WE_SLAVE_RATIO 0x106
+
+static void ddr3_wait (uint32 del)
+{
+ volatile unsigned int i;
+
+ for (i = 0; i < del; i++);
+
+}
+
/*************************************************************************************************
* FUNCTION PUROPSE: Initial EMIF4 setup
*************************************************************************************************
*************************************************************************************************/
SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
{
- UINT32 v, i;
-
-#if 0
- /* If the config registers or refresh control registers are being written
- * disable the initialization sequence until they are all setup */
- if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0) {
-
- v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
- EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
- }
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
-
- /* Allow the configuration to occur */
- v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
- EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
-
- if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
-
- v = cfg->sdRamRefreshCtl;
- EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
- DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-#endif
-
+ UINT32 v, i, TEMP;
+
v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+
+ if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
+ (v == DEVICE_C6670_JTAG_ID_VAL) )
+ {
+ /* 1333 MHz data rate */
+ /***************** 2.2 DDR3 PLL Configuration ************/
+ DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
+ DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
+ DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ
+ ddr3_wait(1000); //Wait for reset to complete
+ DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit
+ ddr3_wait(1000); //Wait for PLL lock
+
+ /**************** 3.0 Leveling Register Configuration ********************/
+ /* Using partial automatic leveling due to errata */
+
+ /**************** 3.2 Invert Clock Out ********************/
+ DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
+ DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
+ DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
+ DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
+ DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
+
+ //Values with invertclkout = 1
+ /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+ DATA0_WRLVL_INIT_RATIO = 0x5E;
+ DATA1_WRLVL_INIT_RATIO = 0x5E;
+ DATA2_WRLVL_INIT_RATIO = 0x5E;
+ DATA3_WRLVL_INIT_RATIO = 0x51;
+ DATA4_WRLVL_INIT_RATIO = 0x38;
+ DATA5_WRLVL_INIT_RATIO = 0x3A;
+ DATA6_WRLVL_INIT_RATIO = 0x24;
+ DATA7_WRLVL_INIT_RATIO = 0x20;
+ DATA8_WRLVL_INIT_RATIO = 0x44;
+
+ DATA0_GTLVL_INIT_RATIO = 0xDD;
+ DATA1_GTLVL_INIT_RATIO = 0xDD;
+ DATA2_GTLVL_INIT_RATIO = 0xBE;
+ DATA3_GTLVL_INIT_RATIO = 0xCA;
+ DATA4_GTLVL_INIT_RATIO = 0xA9;
+ DATA5_GTLVL_INIT_RATIO = 0xA7;
+ DATA6_GTLVL_INIT_RATIO = 0x9E;
+ DATA7_GTLVL_INIT_RATIO = 0xA1;
+ DATA8_GTLVL_INIT_RATIO = 0xBA;
+
+ //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
+ DDR_DDRPHYC &= ~(0x00008000);
+ DDR_DDRPHYC |= (0x00008000);
+ DDR_DDRPHYC &= ~(0x00008000);
+
+ /***************** 2.3 Basic Controller and DRAM configuration ************/
+ DDR_SDRFC = 0x00005162; // enable configuration
+
+ /* DDR_SDTIM1 = 0x1113783C; */
+ TEMP = 0;
+ TEMP |= 0x8 << 25; // T_RP bit field 28:25
+ TEMP |= 0x8 << 21; // T_RCD bit field 24:21
+ TEMP |= 0x9 << 17; // T_WR bit field 20:17
+ TEMP |= 0x17 << 12; // T_RAS bit field 16:12
+ TEMP |= 0x20 << 6; // T_RC bit field 11:6
+ TEMP |= 0x7 << 3; // T_RRD bit field 5:3
+ TEMP |= 0x4; // T_WTR bit field 2:0
+ DDR_SDTIM1 = TEMP;
+
+ /* DDR_SDTIM2 = 0x304F7FE3; */
+ TEMP = 0;
+ TEMP |= 0x3 << 28; // T_XP bit field 30:28
+ TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
+ TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
+ TEMP |= 0x4 << 3; // T_RTP bit field 5:3
+ TEMP |= 0x3; // T_CKE bit field 2:0
+ DDR_SDTIM2 = TEMP;
+
+ /* DDR_SDTIM3 = 0x559F849F; */
+ TEMP = 0;
+ TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
+ TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
+ TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
+ TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
+ TEMP |= 0x49 << 4; // T_RFC bit field 12:4
+ TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
+ DDR_SDTIM3 = TEMP;
- /*KICK0 = 0x83E70B13;
- KICK1 = 0x95A4F1E0;*/
+ DDR_DDRPHYC = 0x0010010F;
+
+ DDR_ZQCFG = 0x70073214;
+
+ DDR_PMCTL = 0x0;
+
+ DDR_SDRFC = 0x00005162; // enable configuration
+
+ /* DDR_SDCFG = 0x63062A32; */
+ /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */
+ TEMP = 0;
+ TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
+ TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
+ TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
+ TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
+ TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
+ TEMP |= 0x2 << 16; // CWL bit field 17:16
+ TEMP |= 0x0 << 14; // NM bit field 15:14
+ TEMP |= 0xA << 10; // CL bit field 13:10
+ TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
+ TEMP |= 0x3 << 4; // IBANK bit field 6:4
+ TEMP |= 0x0 << 3; // EBANK bit field 3:3
+ TEMP |= 0x2; // PAGESIZE bit field 2:0
+ DDR_SDCFG = TEMP;
+
+ ddr3_wait(1000); //Wait 600us for HW init to complete
+
+ DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz]
+
+ DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
+
+ /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
+ Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
+ Actual time = ~10-15 ms */
+ DDR_RDWR_LVL_CTRL = 0x80000000;
- if (v == DEVICE_C6618_JTAG_ID_VAL)
+ ddr3_wait(1000); //Wait 3ms for leveling to complete
+ }
+ else
{
- DDR3PLLCTL0 = 0x100807C1;
+ /* C64x configuration */
+ /* If the config registers or refresh control registers are being written
+ * disable the initialization sequence until they are all setup */
+ if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0) {
+
+ v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+ EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+ }
- DDR_SDTIM1 = 0x0CCF369B;
- DDR_SDTIM2 = 0x3A3F7FDA;
- DDR_SDTIM3 = 0x057F83A8;
- DDR_PMCTL |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
- DDR_DDRPHYC = 0x0010010B;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
- DDR_SDRFC = 0x00004111; //500us
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
- DDR_SDCFG = 0x63C51A32; //0x63C51A32; //row-col = 13-10
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
- //Values with invertclkout = 0
- DATA0_GTLVL_INIT_RATIO = 0x3C;
- DATA1_GTLVL_INIT_RATIO = 0x3C;
- DATA2_GTLVL_INIT_RATIO = 0x23;
- DATA3_GTLVL_INIT_RATIO = 0x2D;
- DATA4_GTLVL_INIT_RATIO = 0x13;
- DATA5_GTLVL_INIT_RATIO = 0x11;
- DATA6_GTLVL_INIT_RATIO = 0x9;
- DATA7_GTLVL_INIT_RATIO = 0xC;
- //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
- //Values with invertclkout = 0
- RDWR_INIT_RATIO_0 = 0x0;
- RDWR_INIT_RATIO_1 = 0x0;
- RDWR_INIT_RATIO_2 = 0x0;
- RDWR_INIT_RATIO_3 = 0x0;
- RDWR_INIT_RATIO_4 = 0x0;
- RDWR_INIT_RATIO_5 = 0x0;
- RDWR_INIT_RATIO_6 = 0x0;
- RDWR_INIT_RATIO_7 = 0x0;
- //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
- //GEL_TextOut("\nProgrammed initial ratios.\n");
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
- DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
- //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
- DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
- //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
-
- DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
- DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead
- //GEL_TextOut("\n Triggered full leveling.\n");
-
- DDR_SDTIM1; //Read MMR to ensure full leveling is complete
-
- DDR_SDRFC = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
- }
- else
- {
- DDR3PLLCTL1 |= 0x00000040; //Set ENSAT = 1
- DDR3PLLCTL1 |= 0x00002000; //Set RESET bit before programming DDR3PLLCTL0
- DDR3PLLCTL0 = 0x02000140;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
- for(i=0;i<1000;i++); //Wait atleast 5us
- DDR3PLLCTL1 &= 0xFFFFDFFF; //Clear RESET bit
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
- DDR_SDRFC = 0x800030D4; // inhibit configuration
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
- DDR_SDTIM1 = 0x0AAAE4E3;
- DDR_SDTIM2 = 0x20437FDA;
- DDR_SDTIM3 = 0x559F83FF;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
- DDR_DDRPHYC = 0x0010010F;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
- DDR_SDRFC = 0x000030D4; // enable configuration
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
- DDR_SDCFG = 0x63222AB2; // DRAM Mode Register writes occur here - 31.25us long refresh periods
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
- DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
- DDR3_CONFIG_REG_0 &= 0xFF801FFF; // clear ctrl_slave_ratio field
- DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio field to 256 since INV_CLKOUT = 1
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
- DDR3_CONFIG_REG_12 |= 0x08000000; // Set INV_CLKOUT = 1
+ /* Allow the configuration to occur */
+ v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+ EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
- DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO | (WR_DQS_SLAVE_RATIO << 10) | (WR_DATA_SLAVE_RATIO << 20);
- DDR3_CONFIG_REG_24 = FIFO_WE_SLAVE_RATIO;
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
+ if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
- DDR_SDRFC = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
+ v = cfg->sdRamRefreshCtl;
+ EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+ DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
}
-
+
return (0);
} /* hwEmif4p0Enable */