#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
+void pass_pll_delay (UINT32 del)
+{
+ UINT32 i;
+ volatile UINT32 j;
+
+ for (i = j = 0; i < del; i++)
+ asm (" nop ");
+
+}
+
/*********************************************************************************************************
* FUNCTION PURPOSE: Configure and enable a pll
* DESCRIPTION: The PLL is configured. If the existing configuration matches the requested one no
* register write is made.
*********************************************************************************************************/
-SINT16 hwPllSetCfgPll (UINT32 base, UINT16 prediv, UINT16 mult, UINT16 postdiv, UINT32 chipFreqMhz, UINT32 pllFreqMhz)
+SINT16 hwPllSetCfgPll (UINT32 base, UINT32 prediv, UINT32 mult, UINT32 postdiv, UINT32 chipFreqMhz, UINT32 pllFreqMhz)
{
UINT32 reg;
UINT32 regb;
currentEnable = BOOT_READ_BITFIELD(regb, 14, 14);
currentClkOut = BOOT_READ_BITFIELD(regb, 13, 13);
- /* The PLL is currently enabled and connected if bypass == 0, enable == 1, clkout == 1 */
-
- if ( (currentBypass == 0) &&
- (currentPrediv == prediv) &&
- (currentMult == mult) &&
- (currentPostdiv == postdiv) &&
- (currentEnable == 0) &&
- (currentClkOut == 1) &&
- (currentBwAdj == (mult >> 1)) )
- return (0);
-
-
/* bwAdj is based only on the mult value */
bwAdj = (mult >> 1) - 1;
- /* Multiplier / divider values are input as 1 less then the desired value */
- if (prediv > 0)
- prediv -= 1;
-
- if (mult > 0)
- mult -= 1;
+ /* Write to the ENSAT bit */
+ regb = BOOT_SET_BITFIELD(regb, 1, 6, 6);
+ DEVICE_REG32_W (base + 4, regb);
- if (postdiv > 0)
- postdiv -= 1;
+ /* Setup the PLL. Assert bypass */
+ reg = BOOT_SET_BITFIELD (reg, 1, 23, 23); /* Bypass must be enabled */
+ DEVICE_REG32_W (base, reg);
/* Set bit 14 in register 1 to disable the PLL (assert reset) */
regb = BOOT_SET_BITFIELD(regb, 1, 14, 14);
+ /* set bit 13 in register 1 for selecting the output of PASS PLL as the input to PASS */
+ regb = BOOT_SET_BITFIELD(regb, 1, 13, 13);
DEVICE_REG32_W (base + 4, regb);
- /* Setup the PLL. Assert bypass */
- reg = BOOT_SET_BITFIELD (reg, prediv, 5, 0);
- reg = BOOT_SET_BITFIELD (reg, mult, 18, 6);
- reg = BOOT_SET_BITFIELD (reg, postdiv, 22, 19);
- reg = BOOT_SET_BITFIELD (reg, 1, 23, 23); /* Bypass must be enabled */
+ reg = BOOT_SET_BITFIELD (reg, prediv - 1, 5, 0);
+ reg = BOOT_SET_BITFIELD (reg, mult - 1, 18, 6);
reg = BOOT_SET_BITFIELD (reg, (bwAdj & 0xff), 31, 24);
DEVICE_REG32_W (base, reg);
DEVICE_REG32_W (base + 4, regb);
- /* Reset must be asserted for at least 5us. Give a huge amount of padding here to be safe
- * (the factor of 100) */
- chipDelay32 (5 * chipFreqMhz * 100);
-
+ /* Reset must be asserted for at least 5us */
+ pass_pll_delay(7000);
/* Clear bit 14 in register 1 to re-enable the pll */
regb = BOOT_SET_BITFIELD(regb, 0, 14, 14);
DEVICE_REG32_W (base + 4, regb);
- /* Need to wait 100,000 output PLL cycles before releasing bypass and setting
- * up the clk output */
- chipDelay32 (chipFreqMhz * 100000 / pllFreqMhz);
-
+ /* Wait for atleast 500 * REFCLK cycles * (PLLD+1) */
+ pass_pll_delay(70000);
/* Disable the bypass */
reg = BOOT_SET_BITFIELD (reg, 0, 23, 23); /* The value 0 disables the bypass */
DEVICE_REG32_W (base, reg);
- /* Enable the output source (set bit 13) */
- regb = BOOT_SET_BITFIELD(regb, 1, 13, 13);
- DEVICE_REG32_W (base + 4, regb);
-
return (0);
} /* hwPllSetCfgPll */