DDR3 and PA SS PLL driver code update

[keystone-rtos/ibl.git] / src / hw / plls / pll014phi / cfgpll2.c

diff --git a/src/hw/plls/pll014phi/cfgpll2.c b/src/hw/plls/pll014phi/cfgpll2.c
index 8c44c1ec4d2d5b62da530593bf2c12692360c5f9..502077b9149c5ac1b3124330ed97a398a08d1a65 100644 (file)
--- a/src/hw/plls/pll014phi/cfgpll2.c
+++ b/src/hw/plls/pll014phi/cfgpll2.c
@@ -21,6 +21,21 @@
 #define BOOT_READ_BITFIELD(z,x,y)   (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
 #define BOOT_SET_BITFIELD(z,f,x,y)  (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
 
+#define CHIP_LEVEL_REG         0x02620000
+#define DDR3PLLCTL0            *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
+#define DDR3PLLCTL1            *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0334)
+
+
+
+void ddr3_pll_delay (UINT32 del)
+{
+  UINT32 i;
+  volatile UINT32 j;
+
+  for (i = j = 0; i < del; i++)
+    asm (" nop ");
+
+}
 
 /*********************************************************************************************************
  * FUNCTION PURPOSE: Configure and enable a pll
@@ -56,7 +71,7 @@ SINT16 hwPllSetCfg2Pll (UINT32 base, UINT32 prediv, UINT32 mult, UINT32 postdiv,
     if ( (currentBypass  == 0)           &&
          (currentPrediv  == prediv)      &&
          (currentMult    == mult)        &&
-         (currentPostdiv == postdiv)     &&
+        (currentPostdiv == postdiv)     &&
          (currentEnable  == 0)           &&
          (currentBwAdj   == (mult >> 1))  )
         return (0);
@@ -75,16 +90,22 @@ SINT16 hwPllSetCfg2Pll (UINT32 base, UINT32 prediv, UINT32 mult, UINT32 postdiv,
     if (postdiv > 0)
         postdiv -= 1;
 
+    /* Write to the ENSAT bit */
+    regb = BOOT_SET_BITFIELD(regb, 1, 6, 6);
+    DEVICE_REG32_W (base + 4, regb);
+
+    /* Bypass must be enabled */
+    reg = BOOT_SET_BITFIELD (reg, 1, 23, 23);
+    DEVICE_REG32_W (base, reg);
+
     /* Set bit 13 in register 1 to disable the PLL (assert reset) */
     regb = BOOT_SET_BITFIELD(regb, 1, 13, 13);
     DEVICE_REG32_W (base + 4, regb);
 
-    /* Setup the PLL. Assert bypass */
-    reg = BOOT_SET_BITFIELD (reg, prediv,          5,  0);
-    reg = BOOT_SET_BITFIELD (reg, mult,           18,  6);
-    reg = BOOT_SET_BITFIELD (reg, postdiv,        22, 19);
-    reg = BOOT_SET_BITFIELD (reg, 1,              23, 23);   /* Bypass must be enabled */
-    reg = BOOT_SET_BITFIELD (reg, (bwAdj & 0xff), 31, 24);
+
+    /* Configure CLKR, CLKF, CLKOD, BWADJ */
+    reg = ((prediv - 1) | ((mult - 1 ) << 6) | (bwAdj << 24));
+
 
     DEVICE_REG32_W (base, reg);
 
@@ -95,7 +116,7 @@ SINT16 hwPllSetCfg2Pll (UINT32 base, UINT32 prediv, UINT32 mult, UINT32 postdiv,
 
     /* Reset must be asserted for at least 5us. Give a huge amount of padding here to be safe
      * (the factor of 100) */
-    chipDelay32 (5 * chipFreqMhz * 100);
+    ddr3_pll_delay(70000);
 
 
     /* Clear bit 13 in register 1 to re-enable the pll */
@@ -104,8 +125,7 @@ SINT16 hwPllSetCfg2Pll (UINT32 base, UINT32 prediv, UINT32 mult, UINT32 postdiv,
 
     /* Need to wait 100,000 output PLL cycles before releasing bypass and setting 
      * up the clk output */
-    chipDelay32 (chipFreqMhz * 100000 / pllFreqMhz);
-
+    ddr3_pll_delay(70000);
 
     /* Disable the bypass */
     reg = BOOT_SET_BITFIELD (reg, 0, 23, 23);   /* The value 0 disables the bypass */