diff --git a/src/ibl.h b/src/ibl.h
index 882ec6ded1f8b63f6ca2773948643c9fce8ff830..6ee3d10e148fa218fe769079ff596bee8e5b1a22 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
#include "types.h"
+
+#define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
+
+
+/**
+ * @brief
+ * The version number, 1.0.0.3
+ */
+#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,3)
+
+
+/**
+ * @defgroup iblBootModes Defines the boot modes supported by the IBL
+ *
+ * @ingroup iblBootModes
+ * @{
+ *
+ * @def ibl_BOOT_MODE_TFTP */
+ #define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */
+
+ /* @def ibl_BOOT_MODE_NAND */
+#define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */
+
+/* @def ibl_BOOT_MODE_NOR */
+#define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */
+
+/* @def ibl_BOOT_MODE_NONE */
+#define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */
+
+/* @} */
+
+/**
+ * @brief
+ * Define the number of different boot modes which can be configured for
+ * a single execution of the IBL.
+ */
+#define ibl_N_BOOT_MODES 2
+
+
/* Information used to make generate a bootp request */
/**
* @brief
*/
#define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
during the ROM boot load process. */
+
+/**
+ * @def ibl_PORT_SWITCH_ALL
+ */
+#define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
+ all ports on the subsystem should be configured */
/**
*/
typedef struct iblEmif4p0_s
{
- uint32 dummy; /**< placeholder */
+ uint32 registerMask; /**< Identifies which registers will be configured */
+ uint32 sdRamConfig; /**< SDRAM Config Register */
+ uint32 sdRamConfig2; /**< SDRAM Config2 Register */
+ uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
+ uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
+ uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
+ uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
+ uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
+ uint32 powerManageCtl; /**< Power Management Control Register */
+ uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
+ uint32 performCountCfg; /**< Performance Counter Config Register */
+ uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
+ uint32 readIdleCtl; /**< Read Idle Control Register */
+ uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
+ uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
+ uint32 tempAlterCfg; /**< Temperature Alert Config Register */
+ uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
+ uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
+ uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
+ uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
+ uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
+ uint32 eccCtl; /**< ECC Control Register */
+ uint32 eccRange1; /**< ECC Address Range 1 Register */
+ uint32 eccRange2; /**< ECC Address Range 2 Register */
+ uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
} iblEmif4p0_t;
+
+/**
+ * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
+ *
+ * @ingroup iblEmif4Select
+ * @{
+ * @def ibl_EMIF4_ENABLE_sdRamConfig
+ */
+#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
+
+/** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
+#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
+
+/** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
+#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
+#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
+#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
+#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
+
+/** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
+#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
+
+/** @def ibl_EMIF4_ENABLE_powerManageCtl */
+#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
+
+/** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
+#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
+
+/** @def ibl_EMIF4_ENABLE_performCountCfg */
+#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
+
+/** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
+#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
+
+/** @def ibl_EMIF4_ENABLE_readIdleCtl */
+#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
+#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
+
+/** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
+#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
+
+/** @def ibl_EMIF4_ENABLE_tempAlterCfg */
+#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
+
+/** @def ibl_EMIF4_ENABLE_priClassSvceMap */
+#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_eccCtl */
+#define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
+
+/** @def ibl_EMIF4_ENABLE_eccRange1 */
+#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
+
+/** @def ibl_EMIF4_ENABLE_eccRange2 */
+#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
+
+/** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
+#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
+
+/** @def ibl_BOOT_EMIF4_ENABLE_ALL */
+#define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
+
+/* @} */
+
+
+/**
+ * @defgroup iblEmifType Defines the EMIF4 type on a device
+ *
+ * @ingroup iblEmifType
+ * @{
+ */
+/** @def ibl_EMIF_TYPE_31 */
+#define ibl_EMIF_TYPE_31 31
+
+/** @def ibl_EMIF_TYPE_40 */
+#define ibl_EMIF_TYPE_40 40
+
+/* @} */
+
/**
* @brief
* This structure is used to configure the DDR interface
*/
typedef struct iblEth_s
{
- uint32 ethPriority; /**< The ethernet boot priority. @ref iblPeriphPriority */
- int32 port; /**< The ethernet port to use, or @ref ibl_ETH_PORT_FROM_RBL */
bool doBootp; /**< If true a bootp request is generated. If false the @ref iblEthBootInfo_t
table must be populated before the ibl begins execution */
bool useBootpServerIp; /**< If TRUE then the server IP received from the bootp server
*/
typedef struct iblSgmii_s
{
- uint32 adviseAbility; /**< The advise ability register */
- uint32 control; /**< The control register */
- uint32 txConfig; /**< Serdes Tx config */
- uint32 rxConfig; /**< Serdes Rx config */
- uint32 auxConfig; /**< Serdes Aux config */
+ bool configure; /**< Set to false to disable configuration */
+ uint32 adviseAbility; /**< The advise ability register */
+ uint32 control; /**< The control register */
+ uint32 txConfig; /**< Serdes Tx config */
+ uint32 rxConfig; /**< Serdes Rx config */
+ uint32 auxConfig; /**< Serdes Aux config */
} iblSgmii_t;
} iblMdio_t;
+/**
+ * @def ibl_N_ECC_BYTES
+ */
+#define ibl_N_ECC_BYTES 6 /**< The number of ECC bytes to be computed for each page */
+
+/**
+ * @def ibl_N_BAD_BLOCK_MARKER
+ */
+#define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
/**
* @brief
uint32 pageOffset; /**< Address bits which specify the page number */
uint32 columnOffset; /**< Address bits which specify the column number */
+ uint32 eccBytesIdx[ibl_N_ECC_BYTES];
+ /**< Index of each ECC byte in each page data */
+ uint32 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
+ /**< Index of bad block marker in each page data */
+
uint8 resetCommand; /**< The command to reset the flash */
uint8 readCommandPre; /**< The read command sent before the address */
uint8 readCommandPost; /**< The read command sent after the address */
typedef struct iblNand_s
{
- uint32 nandPriority; /**< The nand boot priority. @ref iblPeriphPriority */
int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+ uint32 bootAddress; /**< The start address for booting */
+ int32 interface; /**< The nand interface @ref iblPmemf */
iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
nandDevInfo_t nandInfo; /** Low level device info */
} iblNand_t;
+
+/**
+ * @brief
+ * Nor boot configuration.
+ */
+typedef struct iblNor_s
+{
+ int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+ uint32 bootAddress; /**< The start address for booting */
+ int32 interface; /**< The nor interface. @ref iblPmemIf */
+ iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+} iblNor_t;
+
+/**
+ * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
+ * valid for all devices
+ *
+ * @ingroup iblPmemIf
+ * @{
+ */
+
+/** @def ibl_PMEM_IF_GPIO - GPIO interface */
+#define ibl_PMEM_IF_GPIO 0
+
+/** @def ibl_PMEM_IF_CHIPSEL_2 */
+#define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
+
+/** @def ibl_PMEM_IF_CHIPSEL_3 */
+#define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
+
+/** @def ibl_PMEM_IF_CHIPSEL_4 */
+#define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
+
+/** @def ibl_PMEM_IF_CHIPSEL_5 */
+#define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
+
+/** @def ibl_PMEM_IF_SPI */
+#define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
+
+/* @} */
+
+
+/**
+ * @brief
+ * EMIF (nand/nor) configuration
+ */
+typedef struct iblEmif_s {
+
+ int16 csSpace; /**< Chip select space, @ref iblPmemIf */
+ int16 busWidth; /**< Bus width, bits */
+ bool waitEnable; /**< Valid only for NOR devices */
+
+} iblEmif_t;
+
+/**
+ * @brief
+ * The maximum number of chip select spaces for emif boot (not ddr) configuration
+ */
+#define ibl_MAX_EMIF_PMEM 2
+
+
+/**
+ * @brief
+ * SPI configuration used for either NOR or NAND
+ */
+typedef struct iblSpi_s
+{
+ int16 addrWidth; /**< 16 or 24 are the only valid values */
+ int16 nPins; /**< 4 or 5 are the only valid values */
+ int16 mode; /**< Clock / data polarities (valid values 0-3) */
+ int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
+ uint16 c2tdelay; /**< Setup time between chip select and the transaction */
+ uint16 busFreqMHz; /**< Bus speed */
+
+} iblSpi_t;
+
/**
/* @} */
+/**
+ * @def iblBoot_t
+ * Configures an ibl boot attempt
+ *
+ * @details
+ * The ibl allows for the configuration for multiple boot attempts. This structure is
+ * used to configure the ibl boot attempt.
+ */
+typedef struct iblBoot_s
+{
+ int32 bootMode; /**< Identifies the boot mode @ref iblBootModes */
+
+ uint32 priority; /**< The boot priority. @ref iblPeriphPriority */
+ int32 port; /**< The port to use, or @ref ibl_PORT_FROM_RBL */
+
+ union {
+
+ iblEth_t ethBoot; /**< Ethernet boot configuration. @ref iblEth_t */
+
+ iblNand_t nandBoot; /**< NAND boot configuration @ref iblNand_t */
+
+ iblNor_t norBoot; /**< NOR boot configuration @ref iblNor_t */
+
+ } u;
+
+} iblBoot_t;
+
/**
* @def ibl_MAGIC_VALUE
*/
typedef struct ibl_s
{
- uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
+ uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
+
+ iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
- iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
+ iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
- iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
+ iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
- iblEth_t ethConfig[ibl_N_ETH_PORTS]; /**< Ethernet boot configuration. @ref iblEth_t */
+ iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
- iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
+ iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
- iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
+ iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
- iblNand_t nandConfig; /**< NAND configuration @ref iblNand_t */
+ iblBoot_t bootModes[ibl_N_BOOT_MODES]; /**< Boot configuration */
+ uint16 chkSum; /**< Ones complement checksum over the whole config structure */
-/* iblI2c_t i2cConfig; */
-/* iblSpi_t spiConfig; */
} ibl_t;
extern ibl_t ibl;
-
/**
- * @defgroup iblActivePeriph
+ * @defgroup iblActiveDevice
*
- * @ingroup iblActivePeriph
+ * @ingroup iblActiveDevice
* @{
- * @def ibl_ACTIVE_PERIPH_ETH
+ * @def ibl_ACTIVE_DEVICE_ETH
*/
-#define ibl_ACTIVE_PERIPH_ETH 100 /**< An ethernet boot in progress */
+#define ibl_ACTIVE_DEVICE_ETH 100 /**< Data received through an ethernet interface */
/**
- * @def ibl_ACTIVE_PERIPH_NAND
+ * @def ibl_ACTIVE_DEVICE_EMIF
*/
-#define ibl_ACTIVE_PERIPH_NAND 101 /**< A nand boot in progress */
+#define ibl_ACTIVE_DEVICE_EMIF 101 /**< Data read through an EMIF interface */
/**
- * @def ibl_ACTIVE_PERIPH_I2C
+ * @def ibl_ACTIVE_DEVICE_I2C
*/
-#define ibl_ACTIVE_PERIPH_I2C 102 /**< An i2c boot in progress */
+#define ibl_ACTIVE_DEVICE_I2C 102 /**< Data read through an I2C interface */
/**
- * @def ibl_ACTIVE_PERIPH_SPI
+ * @def ibl_ACTIVE_DEVICE_SPI
*/
-#define ibl_ACTIVE_PERIPH_SPI 103 /**< An SPI boot in progress */
+#define ibl_ACTIVE_DEVICE_SPI 103 /**< Data read through an SPI interface */
/* @} */
+/**
+ * @defgroup iblFailCode
+ *
+ * @ingroup iblFailCode
+ * @{
+ * @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
+ */
+#define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 /**< Invalid i2c eeprom address encountered */
+
+/**
+ * @def ibl_FAIL_CODE_BTBL_FAIL
+ */
+#define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
+
+/**
+ * @def ibl_FAIL_CODE_PA
+ */
+#define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
+
+
+/**
+ * @def ibl_FAIL_CODE_SPI_PARAMS
+ */
+#define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_INIT_DEVICE
+ */
+#define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 /**< Second stage boot device specified is invalid */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_SPI_ADDRESS
+ */
+#define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 /**< Invalid data address specified on SPI */
+
+/**
+ * @def ibl_FAIL_CODE_PERIPH_POWER_UP
+ */
+#define ibl_FAIL_CODE_PERIPH_POWER_UP 706 /**< Boot peripheral failed to power up */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_NAND_PERIPH
+ */
+#define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 /**< Invalid nand boot peripheral specified */
+
+/**
+ * @def ibl_FAIL_CODE_NO_EMIF_CFG
+ */
+#define ibl_FAIL_CODE_NO_EMIF_CFG 708 /**< No emif configuration found to match specified cs space */
+
+/**
+ * @def ibl_FAIL_CODE_EMIF_CFG_FAIL
+ */
+#define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 /**< Hardware setup of emif failed */
+
+ /* @} */
+
+
/**
* @brief
* Provide status on the boot operation
{
uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
- int32 tableLoadFail; /**< If non-zero then the load of the parameter table from i2c failed */
+ uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
+
+ uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
+
+ uint32 i2cRetries; /**< Count of I2C read retries */
+ uint32 i2cDataRetries; /**< Number of retries while reading block data from the i2c */
+
+ uint32 spiRetries; /**< Count of SPI read retries */
+ uint32 spiDataRetries; /**< Number of retries while reading block data from the spi */
+
+ uint32 magicRetries; /**< Count of I2C/SPI re-reads because the magic number was incorrect */
+ uint32 mapSizeFail; /**< Number of times an invalid map table size was read from the i2c/spi */
+ uint32 mapRetries; /**< Number of times the checksum failed on the read of the i2c/spi map */
int32 heartBeat; /**< An increasing value as long as the boot code is running */
- int32 noMagic; /**< A non-zero value here indicates that @ref ibl_MAGIC_VALUE was not found
- in the @ref ibl_t magic field, and default values were loaded. */
- int32 activePeriph; /**< Describes the active boot peripheral @ref iblActivePeriph */
- int32 activeFormat; /**< Describes the format being decoded */
- int32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
- int32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
+ int32 activeBoot; /**< Describes the active boot mode @ref iblBootModes */
+ int32 activeDevice; /**< Describes the active boot peripheral device @ref iblActiveDevice */
+ int32 activeFileFormat; /**< Describes the format being decoded */
- int32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
+ uint32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
+ uint32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
+
+ uint32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
uint32 exitAddress; /**< If non-zero the IBL exited and branched to this address */
extern iblStatus_t iblStatus;
+/**
+ * @brief
+ * The ibl boot map structure
+ *
+ * @details
+ * The ibl boot device contains a structure which identifies the location of the big and little
+ * endian ibl images on the external device.
+ */
+typedef struct iblBootMap_s
+{
+ uint16 length; /**< Size of the structure in bytes */
+ uint16 chkSum; /**< Value which makes the ones complement checksum over the block equal to 0 or -0 */
+
+ uint32 addrLe; /**< Base address of the boot tables for the little endian image */
+ uint32 configLe; /**< Base address of the ibl structure for use with the little endian image */
+
+ uint32 addrBe; /**< Base address of the boot tables for the big endian image */
+ uint32 configBe; /**< Base address of the ibl structure for use with the big endian image */
+
+} iblBootMap_t;
+