diff --git a/src/ibl.h b/src/ibl.h
index 5b0e0b9c62a6a153455f1af82042418f2bc2eb44..d09fbfabf0f3e89e3a9b22b510281eedeb907d71 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
/********************************************************************************************************
* FILE PURPOSE: IBL configuration and control definitions
********************************************************************************************************
#include "types.h"
+
+#define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
+
+
+/**
+ * @brief
+ * The version number, 1.0.0.0
+ */
+#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,0)
+
/* Information used to make generate a bootp request */
/**
* @brief
*/
#define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
during the ROM boot load process. */
+
+/**
+ * @def ibl_PORT_SWITCH_ALL
+ */
+#define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
+ all ports on the subsystem should be configured */
/**
*/
typedef struct iblEmif4p0_s
{
- uint32 dummy; /**< placeholder */
+ uint32 registerMask; /**< Identifies which registers will be configured */
+ uint32 sdRamConfig; /**< SDRAM Config Register */
+ uint32 sdRamConfig2; /**< SDRAM Config2 Register */
+ uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
+ uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
+ uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
+ uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
+ uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
+ uint32 powerManageCtl; /**< Power Management Control Register */
+ uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
+ uint32 performCountCfg; /**< Performance Counter Config Register */
+ uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
+ uint32 readIdleCtl; /**< Read Idle Control Register */
+ uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
+ uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
+ uint32 tempAlterCfg; /**< Temperature Alert Config Register */
+ uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
+ uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
+ uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
+ uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
+ uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
+ uint32 eccCtl; /**< ECC Control Register */
+ uint32 eccRange1; /**< ECC Address Range 1 Register */
+ uint32 eccRange2; /**< ECC Address Range 2 Register */
+ uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
} iblEmif4p0_t;
+
+/**
+ * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
+ *
+ * @ingroup iblEmif4Select
+ * @{
+ * @def ibl_EMIF4_ENABLE_sdRamConfig
+ */
+#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
+
+/** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
+#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
+
+/** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
+#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
+#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
+#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
+#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
+
+/** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
+#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
+
+/** @def ibl_EMIF4_ENABLE_powerManageCtl */
+#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
+
+/** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
+#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
+
+/** @def ibl_EMIF4_ENABLE_performCountCfg */
+#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
+
+/** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
+#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
+
+/** @def ibl_EMIF4_ENABLE_readIdleCtl */
+#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
+#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
+
+/** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
+#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
+
+/** @def ibl_EMIF4_ENABLE_tempAlterCfg */
+#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
+
+/** @def ibl_EMIF4_ENABLE_priClassSvceMap */
+#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_eccCtl */
+#define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
+
+/** @def ibl_EMIF4_ENABLE_eccRange1 */
+#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
+
+/** @def ibl_EMIF4_ENABLE_eccRange2 */
+#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
+
+/** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
+#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
+
+/** @def BOOT_EMIF4_ENABLE_ALL */
+#define BOOT_EMIF4_ENABLE_ALL 0x007fffff
+
+/* @} */
+
+
+/**
+ * @defgroup iblEmifType Defines the EMIF4 type on a device
+ *
+ * @ingroup iblEmifType
+ * @{
+ */
+/** @def ibl_EMIF_TYPE_31 */
+#define ibl_EMIF_TYPE_31 31
+
+/** @def ibl_EMIF_TYPE_40 */
+#define ibl_EMIF_TYPE_40 40
+
+/* @} */
+
/**
* @brief
* This structure is used to configure the DDR interface
uint32 nandPriority; /**< The nand boot priority. @ref iblPeriphPriority */
int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+ int32 interface; /**< The nand interface @ref iblNandIf */
iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
nandDevInfo_t nandInfo; /** Low level device info */
} iblNand_t;
+
+/**
+ * @defgroup iblNandIf defines the interface used for NAND memory. Not all values
+ * are valid for all devices.
+ *
+ * @ingroup iblNandIf
+ * @{
+ */
+/** @def ibl_NAND_IF_GPIO - GPIO interface */
+#define ibl_NAND_IF_GPIO 0
+
+/** @def ibl_NAND_IF_CHIPSEL_2 - EMIF interface using chip select 2 */
+#define ibl_NAND_IF_CHIPSEL_2 2
+
+/** @def ibl_NAND_IF_CHIPSEL_3 - EMIF interface using chip select 3 */
+#define ibl_NAND_IF_CHIPSEL_3 3
+
+/** @def ibl_NAND_IF_CHIPSEL_4 - EMIF interface using chip select 4 */
+#define ibl_NAND_IF_CHIPSEL_4 4
+
+/** @def ibl_NAND_IF_CHIPSEL_5 - EMIF interface using chip select 5 */
+#define ibl_NAND_IF_CHIPSEL_5 5
+
+/** @def ibl_NAND_IF_SPI - NAND interface through SPI */
+#define ibl_NAND_IF_SPI 100
+
+
+/* @} */
+
+
+/**
+ * @brief
+ * SPI configuration used for either NOR or NAND
+ */
+typedef struct iblSpi_s
+{
+ int16 addrWidth; /**< 16 or 24 are the only valid values */
+ int16 nPins; /**< 4 or 5 are the only valid values */
+ int16 mode; /**< Clock / data polarities (valid values 0-3) */
+ int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
+ uint16 c2tdelay; /**< Setup time between chip select and the transaction */
+ uint16 busFreqMHz; /**< Bus speed */
+
+} iblSpi_t;
+
/**
iblNand_t nandConfig; /**< NAND configuration @ref iblNand_t */
- uint16 chkSum; /**< Ones complement checksum over the whole config structure */
+ iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
+ uint16 chkSum; /**< Ones complement checksum over the whole config structure */
-/* iblI2c_t i2cConfig; */
-/* iblSpi_t spiConfig; */
} ibl_t;
*/
#define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
+/**
+ * @def ibl_FAIL_CODE_PA
+ */
+#define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
+
+
+/**
+ * @def ibl_FAIL_CODE_SPI_PARAMS
+ */
+#define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
+
/* @} */
{
uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
+ uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
+
uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
uint32 i2cRetries; /**< Count of I2C read retries */