Modified IBL to re-init PLL in DDR controller, added UART

[keystone-rtos/ibl.git] / src / main / c64x / make / makefile

diff --git a/src/main/c64x/make/makefile b/src/main/c64x/make/makefile
index 0d29e1a35a0d5642e8e2edaddad09bd899e2ea5c..b546c601ed3224e1e22b5994988dafcf69fffa84 100644 (file)
--- a/src/main/c64x/make/makefile
+++ b/src/main/c64x/make/makefile
@@ -74,6 +74,7 @@ C6X_C_DIR+= ;$(IBL_ROOT)/nandboot
 C6X_C_DIR+= ;$(IBL_ROOT)/norboot
 C6X_C_DIR+= ;$(IBL_ROOT)/driver/timer
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/i2c
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/uart/c66x_uart
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/spi
 C6X_C_DIR+= ;$(IBL_ROOT)/cfg/$(TARGET)
 C6X_C_DIR+= ;$(STDINC)