diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 7c8986bab57fa6a789946191da4837739bf306a0..0dc44a8167524799d008bb871b5f42bb3f577b24 100644 (file)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
#include "device.h"
#include "ethboot.h"
#include "nandboot.h"
+#include "norboot.h"
#include "bis.h"
#include "coffwrap.h"
#include "iblbtbl.h"
#include "iblblob.h"
#include "timer.h"
#include "i2c.h"
+#include "spi_api.h"
#include "ibl_elf.h"
#include <string.h>
+extern cregister unsigned int IER;
+
+uint32 iblEndianIdx = 0;
+uint32 iblImageIdx = 0;
+
/**
* @brief
* Data structures shared between the 1st and 2nd stage IBL load
}
+/**
+ * @b Description
+ * @n
+ *
+ * For NAND and NOR boots, configure the specified peripheral or memory interface
+ */
+void iblPmemCfg (int32 interface, int32 port, bool enableNand)
+{
+ int32 ret;
+
+ switch (interface) {
+
+ #if (!defined(EXCLUDE_NAND_GPIO))
+
+ case ibl_PMEM_IF_GPIO:
+ ret = devicePowerPeriph (TARGET_PWR_GPIO);
+ break;
+ #endif
+
+ #if (!defined(EXCLUDE_NOR_SPI) && !defined(EXCLUDE_NAND_SPI))
+
+ case ibl_PMEM_IF_SPI: {
+
+ Uint32 v;
+ spiConfig_t cfg;
+
+ ret = devicePowerPeriph (TARGET_PWR_SPI);
+ if (ret != 0)
+ break;
+
+ cfg.port = port;
+ cfg.mode = ibl.spiConfig.mode;
+ cfg.addrWidth = ibl.spiConfig.addrWidth;
+ cfg.npin = ibl.spiConfig.nPins;
+ cfg.csel = ibl.spiConfig.csel;
+ cfg.c2tdelay = ibl.spiConfig.c2tdelay;
+
+ /* On c66x devices the PLL module has a built in divide by 6, and the SPI
+ * has a maximum clock divider value of 0xff */
+ v = ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz / (DEVICE_SPI_MOD_DIVIDER * ibl.spiConfig.busFreqMHz);
+ if (v > 0xff)
+ v = 0xff;
+
+ cfg.clkdiv = (UINT16) v;
+
+ ret = hwSpiConfig (&cfg);
+ if (ret != 0) {
+ iblStatus.iblFail = ibl_FAIL_CODE_SPI_PARAMS;
+ return;
+ }
+
+ }
+ break;
+ #endif
+
+ #if (!defined(EXCLUDE_NOR_EMIF) || !defined(EXCLUDE_NAND_EMIF))
+
+ case ibl_PMEM_IF_CHIPSEL_2:
+ case ibl_PMEM_IF_CHIPSEL_3:
+ case ibl_PMEM_IF_CHIPSEL_4:
+ case ibl_PMEM_IF_CHIPSEL_5: {
+
+ int i;
+
+ /* Locate the configuration corresponding to this chip select space */
+ for (i = 0; i < ibl_MAX_EMIF_PMEM; i++)
+ if (ibl.emifConfig[i].csSpace == interface)
+ break;
+
+ if (i == ibl_MAX_EMIF_PMEM) {
+ iblStatus.iblFail = ibl_FAIL_CODE_NO_EMIF_CFG;
+ return;
+ }
+
+ ret = devicePowerPeriph (TARGET_PWR_EMIF);
+ if (ret != 0)
+ break;
+
+ if (hwEmif25Init (interface, ibl.emifConfig[i].busWidth, ibl.emifConfig[i].waitEnable, enableNand) != 0)
+ iblStatus.iblFail = ibl_FAIL_CODE_EMIF_CFG_FAIL;
+
+ }
+ break;
+
+ #endif
+
+ default:
+
+
+
+ iblStatus.iblFail = ibl_FAIL_CODE_INVALID_NAND_PERIPH;
+ return;
+ }
+
+ if (ret != 0) {
+ iblStatus.iblFail = ibl_FAIL_CODE_PERIPH_POWER_UP;
+ return;
+ }
+
+}
+
+
/**
* @b Description
void main (void)
{
int32 i, j;
+ UINT32 v, boot_mode_idx, boot_para_idx;
/* Initialize the status structure */
iblMemset (&iblStatus, 0, sizeof(iblStatus_t));
timer_init ();
/* Load default mac addresses for ethernet boot if requested */
- for (i = 0; i < ibl_N_ETH_PORTS; i++) {
+ for (i = 0; i < ibl_N_BOOT_MODES; i++) {
- if ( (iblPriorityIsValid (ibl.ethConfig[i].ethPriority) ) &&
- (iblMacAddrIsZero (ibl.ethConfig[i].ethInfo.hwAddress) ) )
+ if (ibl.bootModes[i].bootMode == ibl_BOOT_MODE_TFTP) {
- deviceLoadDefaultEthAddress (ibl.ethConfig[i].ethInfo.hwAddress);
+ if (iblMacAddrIsZero (ibl.bootModes[i].u.ethBoot.ethInfo.hwAddress))
+ deviceLoadDefaultEthAddress (ibl.bootModes[i].u.ethBoot.ethInfo.hwAddress);
+ }
}
/* Try booting forever */
for (;;) {
- /* Start looping through the boot modes to find the one with the lowest priority
- * value, and try to boot it. If a boot mode is not supported the function
- * statement is simply defined to be a void statement */
- for (i = ibl_HIGHEST_PRIORITY; i < ibl_LOWEST_PRIORITY; i++) {
-
-#ifndef EXCLUDE_ETH
- for (j = 0; j < ibl_N_ETH_PORTS; j++) {
- if (ibl.ethConfig[j].ethPriority == i) {
- iblStatus.activePeriph = ibl_ACTIVE_PERIPH_ETH;
- memcpy (&iblStatus.ethParams, &ibl.ethConfig[j].ethInfo, sizeof (iblEthBootInfo_t));
- iblEthBoot (j);
+#ifndef EXCLUDE_MULTI_BOOT
+ v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+ if (
+ (v == DEVICE_C6678_JTAG_ID_VAL) ||
+ (v == DEVICE_C6670_JTAG_ID_VAL)
+ )
+ {
+ IER = 0;
+
+ /* For C66x devices, check the DEVSTAT register to find which image on which device to boot. */
+ v = DEVICE_REG32_R(DEVICE_REG_DEVSTAT);
+
+ /* Get the Endianness */
+ if (ibl_N_ENDIANS == 1)
+ {
+ iblEndianIdx = 0;
+ }
+ else
+ {
+ if (v & ibl_ENDIAN_LITTLE)
+ {
+ iblEndianIdx = 0;
+ }
+ else
+ {
+ iblEndianIdx = 1;
}
}
-#endif
-#ifndef EXCLUDE_NAND
- if (ibl.nandConfig.nandPriority == i) {
- iblStatus.activePeriph = ibl_ACTIVE_PERIPH_NAND;
- iblNandBoot ();
+ /* Get the boot mode index */
+ boot_para_idx = BOOT_READ_BITFIELD(v,8,4);
+
+ /* Only 1 image supported for TFTP boot */
+ if (boot_para_idx > (ibl_N_IMAGES*(ibl_N_BOOT_MODES-1)))
+ {
+ /* boot parameter index not supported */
+ continue;
}
-#endif
+ boot_mode_idx = boot_para_idx/ibl_N_IMAGES;
+ /* Get the boot image index */
+ iblImageIdx = boot_para_idx & (ibl_N_IMAGES - 1);
+ iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
+
+ switch (ibl.bootModes[boot_mode_idx].bootMode)
+ {
+#ifndef EXCLUDE_ETH
+ case ibl_BOOT_MODE_TFTP:
+ iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+ iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[boot_mode_idx].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+ iblEthBoot (boot_mode_idx);
+ break;
+#endif
+
+#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
+ case ibl_BOOT_MODE_NAND:
+ iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+ memset ((void *)0x80000000, 0, 0x20000000);
+ iblNandBoot (boot_mode_idx);
+ break;
+#endif
+
+#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
+ case ibl_BOOT_MODE_NOR:
+ iblPmemCfg (ibl.bootModes[boot_mode_idx].u.norBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+ iblNorBoot (boot_mode_idx);
+ break;
+#endif
+ }
iblStatus.heartBeat += 1;
}
-
+ else
+#endif
+ {
+
+ /* For C64x devices, loop through the boot modes to find the one with the highest priority
+ * value, and try to boot it. */
+ for (i = ibl_HIGHEST_PRIORITY; i < ibl_LOWEST_PRIORITY; i++) {
+
+ for (j = 0; j < ibl_N_BOOT_MODES; j++) {
+
+ if (ibl.bootModes[j].priority == i) {
+
+ iblStatus.activeBoot = ibl.bootModes[j].bootMode;
+
+ switch (ibl.bootModes[j].bootMode) {
+
+
+#ifndef EXCLUDE_ETH
+ case ibl_BOOT_MODE_TFTP:
+ iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+ iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[j].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+ iblEthBoot (j);
+ break;
+#endif
+
+#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
+ case ibl_BOOT_MODE_NAND:
+ iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
+ iblNandBoot (j);
+ break;
+#endif
+
+#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
+ case ibl_BOOT_MODE_NOR:
+ iblPmemCfg (ibl.bootModes[j].u.norBoot.interface, ibl.bootModes[j].port, TRUE);
+ iblNorBoot (j);
+ break;
+#endif
+
+ }
+ }
+
+ iblStatus.heartBeat += 1;
+
+ }
+ }
+ }
}
@@ -238,7 +443,7 @@ Uint32 iblBoot (BOOT_MODULE_FXN_TABLE *bootFxn, Int32 dataFormat, void *formatPa
}
- iblStatus.activeFormat = dataFormat;
+ iblStatus.activeFileFormat = dataFormat;
/* Invoke the parser */