diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 6cd57996e3965de4f10db7fcb089de19b123c0e5..cbbcad73c610b897bd8a96300a056200107fefd8 100644 (file)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
cfg.csel = ibl.spiConfig.csel;
cfg.c2tdelay = ibl.spiConfig.c2tdelay;
- /* On c661x devices the PLL module has a built in divide by 6, and the SPI
+ /* On c66x devices the PLL module has a built in divide by 6, and the SPI
* has a maximum clock divider value of 0xff */
v = ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz / (DEVICE_SPI_MOD_DIVIDER * ibl.spiConfig.busFreqMHz);
if (v > 0xff)
{
int32 i, j;
UINT32 v, boot_mode_idx, boot_para_idx;
+ unsigned int dip_setting;
/* Initialize the status structure */
iblMemset (&iblStatus, 0, sizeof(iblStatus_t));
#ifndef EXCLUDE_MULTI_BOOT
v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
if (
- (v == DEVICE_C6618_JTAG_ID_VAL) ||
- (v == DEVICE_C6616_JTAG_ID_VAL)
+ (v == DEVICE_C6678_JTAG_ID_VAL) ||
+ (v == DEVICE_C6670_JTAG_ID_VAL)
)
{
IER = 0;
}
boot_mode_idx = boot_para_idx/ibl_N_IMAGES;
/* Get the boot image index */
- iblImageIdx == boot_para_idx & (ibl_N_IMAGES - 1);
+ iblImageIdx = boot_para_idx & (ibl_N_IMAGES - 1);
iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
break;
#endif
-#if ((!defined(EXCLUDE_NAND_EMIF)) )
+#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
memset ((void *)0x80000000, 0, 0x20000000);
}
iblStatus.heartBeat += 1;
}
- else
-#endif
- {
-
- /* For C64x devices, loop through the boot modes to find the one with the highest priority
- * value, and try to boot it. */
- for (i = ibl_HIGHEST_PRIORITY; i < ibl_LOWEST_PRIORITY; i++) {
-
- for (j = 0; j < ibl_N_BOOT_MODES; j++) {
-
- if (ibl.bootModes[j].priority == i) {
-
- iblStatus.activeBoot = ibl.bootModes[j].bootMode;
-
- switch (ibl.bootModes[j].bootMode) {
-
-
+#else
+
+ dip_setting = get_device_switch_setting();
+
+ if (dip_setting == 0)
+ boot_mode_idx = 0;
+ else if (dip_setting == 1)
+ boot_mode_idx = 1;
+
+ iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
+
+ switch (ibl.bootModes[boot_mode_idx].bootMode) {
#ifndef EXCLUDE_ETH
- case ibl_BOOT_MODE_TFTP:
- iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
- iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[j].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
- iblEthBoot (j);
- break;
+ case ibl_BOOT_MODE_TFTP:
+ iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+ iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[boot_mode_idx].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+ iblEthBoot (boot_mode_idx);
+ break;
#endif
-#if ((!defined(EXCLUDE_NAND_EMIF)) )
- case ibl_BOOT_MODE_NAND:
- iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
- iblNandBoot (j);
- break;
+#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
+ case ibl_BOOT_MODE_NAND:
+ iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+ iblNandBoot (boot_mode_idx);
+ break;
#endif
-
-#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
- case ibl_BOOT_MODE_NOR:
- iblPmemCfg (ibl.bootModes[j].u.norBoot.interface, ibl.bootModes[j].port, TRUE);
- iblNorBoot (j);
- break;
+ }
+ iblStatus.heartBeat += 1;
#endif
-
- }
- }
-
- iblStatus.heartBeat += 1;
-
- }
- }
- }
- }
-
+ }
} /* main */