Modified IBL to re-init PLL in DDR controller, added UART

[keystone-rtos/ibl.git] / src / make / ibl_c66x / ibl_objs_template.inc

diff --git a/src/make/ibl_c66x/ibl_objs_template.inc b/src/make/ibl_c66x/ibl_objs_template.inc
index c39b57d1ed4fced5a69e7f8c168a9a34970e6c0a..1d6a7b36d2422a644df55977ce402dc48cb94191 100644 (file)
--- a/src/make/ibl_c66x/ibl_objs_template.inc
+++ b/src/make/ibl_c66x/ibl_objs_template.inc
@@ -14,7 +14,7 @@
 ../hw/c64x/make/pll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
 ../hw/c64x/make/pll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc

-
+../hw/c64x/make/evmc66x_uart.ENDIAN_TAG.oc

 
 #ifndef EXCLUDE_BIS
 ../interp/c64x/make/bis.ENDIAN_TAG.oc
 
 #ifndef EXCLUDE_BIS
 ../interp/c64x/make/bis.ENDIAN_TAG.oc