index 64fa4784935d8e300bb3930cbe7fee7e72d9cc6d..392dd31bfca533b5ade1fc97931954a6bace35b8 100755 (executable)
#define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
#define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
#define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
+#define ibl_EVM_C6474M 0x41 /**< C6474 Mez EVM */
#define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
#define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
hotmenu setConfig_c6472()
{
ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6472L;
ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
/* SGMII not present */
- ibl.sgmiiConfig[0].configure = FALSE;
- ibl.sgmiiConfig[1].configure = FALSE;
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 8;
/* spiConfig and emifConfig not needed */
/* Ethernet configuration for Boot mode 0 */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
/* Bootp is disabled. The server and file name are provided here */
ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
/* Even though the entire range of DDR2 is chosen, the load will
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,103,200);
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,103,58);
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,103,1);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,113);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
/* Leave the hardware address as 0 so the e-fuse value will be used */
ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
+
ibl.chkSum = 0;
}
hotmenu setConfig_c6474()
{
ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6474M;
ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
/* SGMII 0 is present */
- ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
/* There is no port 1 on the 6474 */
- ibl.sgmiiConfig[1].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 8;
/* spiConfig and emifConfig not needed */
/* Ethernet configuration for Boot mode 0 */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
/* Bootp is disabled. The server and file name are provided here */
ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 10,218,109,35);
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
/* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
hotmenu setConfig_c6474lite()
{
ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6474L;
ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
/* SGMII 0 is present */
- ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000e23;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
/* There is no port 1 on the 6474 */
- ibl.sgmiiConfig[1].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 5;
/* spiConfig and emifConfig not needed */
/* Ethernet configuration for Boot mode 0 */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
/* Bootp is disabled. The server and file name are provided here */
ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,114);
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
hotmenu setConfig_c6457()
{
ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6457L;
ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
/* SGMII 0 is present */
- ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000e21;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
/* There is no port 1 on the 6457 */
- ibl.sgmiiConfig[1].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 5;
ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
- ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
/* spiConfig and emifConfig not needed */
/* Ethernet configuration for Boot mode 0 */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
/* Bootp is disabled. The server and file name are provided here */
ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,115);
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
hotmenu setConfig_c6455()
{
ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6455L;
ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
/* SGMII not present */
- ibl.sgmiiConfig[0].configure = FALSE;
- ibl.sgmiiConfig[1].configure = FALSE;
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 0;
/* spiConfig and emifConfig not needed */
/* Ethernet configuration for Boot mode 0 */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
/* Bootp is disabled. The server and file name are provided here */
ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,118);
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
/* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
- ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
ibl.bootModes[1].port = 0;
ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
- ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
- ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[2].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[2].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
- ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
- ibl.chkSum = 0;
+ ibl.chkSum = 0;
}
menuitem "EVM c6670 IBL";
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
/* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 12;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
- ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
ibl.bootModes[1].port = 0;
- ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
- ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
- ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[2].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[2].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
- ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
- ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
- ibl.chkSum = 0;
+ ibl.chkSum = 0;
}