index 7f617d956fe4b8cb10c5c55f829575de94a0941a..392dd31bfca533b5ade1fc97931954a6bace35b8 100755 (executable)
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
/* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 12;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;