index fba6a7d8ecfa243fab5d688f1e1ff66280640e4b..3f33d1e3a38b43761206c1119ecf6fc554aaf1c1 100755 (executable)
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
/* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 12;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;