index 0647a152f0ba7c0b6452c9c6aa041573ac9e7cac..7f617d956fe4b8cb10c5c55f829575de94a0941a 100755 (executable)
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,103,200);
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,103,58);
- SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,103,1);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,113);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
/* Leave the hardware address as 0 so the e-fuse value will be used */
ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
+
ibl.chkSum = 0;
}
ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
- ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
/* spiConfig and emifConfig not needed */
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
- ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
/* spiConfig and emifConfig not needed */
ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- /* Alternative bootMode not configured for now */
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
ibl.chkSum = 0;
}
ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* Image size (10 MB) */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
ibl.chkSum = 0;
ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size mode */
ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* Image size (10 MB) */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
ibl.chkSum = 0;