index 3cbe2ef163ab960d0760d0216dea8e6834fadcd3..8e83d967cb4c5ceeca6d7ec6ccaeabf431dcebe7 100644 (file)
\r
}\r
\r
+menuitem "EVM c6457 EVM IBL";\r
+\r
+hotmenu setConfig_c6457()\r
+{\r
+ ibl.iblMagic = ibl_MAGIC_VALUE;\r
+\r
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
+\r
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
+\r
+ /* The network PLL. The multipliers/dividers are fixed */\r
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
+\r
+ /* EMIF configuration */\r
+ ibl.ddrConfig.configDdr = TRUE;\r
+\r
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */ \r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x3d44c742; /* Timing 2 */\r
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
+\r
+\r
+ /* Ethernet configuration for port 0 */\r
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
+ ibl.ethConfig[0].port = 0;\r
+\r
+ /* Bootp is disabled. The server and file name are provided here */\r
+ ibl.ethConfig[0].doBootp = FALSE;\r
+ ibl.ethConfig[0].useBootpServerIp = FALSE;\r
+ ibl.ethConfig[0].useBootpFileName = FALSE;\r
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,115);\r
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
+\r
+ /* Set the hardware address as 0 so the e-fuse value will be used */\r
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
+\r
+\r
+ ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
+ ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
+ ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
+ ibl.ethConfig[0].ethInfo.fileName[3] = '5';\r
+ ibl.ethConfig[0].ethInfo.fileName[4] = '7';\r
+ ibl.ethConfig[0].ethInfo.fileName[5] = '-';\r
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'e';\r
+ ibl.ethConfig[0].ethInfo.fileName[8] = '.';\r
+ ibl.ethConfig[0].ethInfo.fileName[9] = 'b';\r
+ ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
+ ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
+\r
+\r
+ /* Even though the entire range of DDR2 is chosen, the load will\r
+ * stop when the ftp reaches the end of the file */\r
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
+\r
+ /* There is no port 1 on the 6457 Lite EVM */\r
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
+\r
+ /* SGMII is present */\r
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
+ ibl.sgmiiConfig[0].control = 0x20;\r
+ ibl.sgmiiConfig[0].txConfig = 0x00000e23;\r
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;\r
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;\r
+\r
+ /* MDIO configuration */\r
+ ibl.mdioConfig.nMdioOps = 8;\r
+ ibl.mdioConfig.mdioClkDiv = 0x26;\r
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
+\r
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
+\r
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
+\r
+\r
+ /* This board has NAND. We will enable later */\r
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
+\r
+}\r
+\r
menuitem "EVM c6455 IBL";\r
\r
hotmenu setConfig_c6455()\r