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(parent: 71dc296) | patch
c66x: DDR3 PLL init update
authorSandeep Paulraj <s-paulraj@ti.com>
Wed, 2 Nov 2011 21:26:31 +0000 (17:26 -0400)
committerSandeep Paulraj <s-paulraj@ti.com>
Wed, 2 Nov 2011 21:26:31 +0000 (17:26 -0400)
commit053bd2efa36bee31775656e1b38924dc39c8740d
treed5ed98c52e36c1e128d4af79f0953ebc6204cbc5tree | snapshot (tar.xz tar.gz zip)
parent71dc296cb9006dc7b7163ae40a49f1e0c2d2d536commit | diff
c66x: DDR3 PLL init update

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/hw/ddrs/emif4/emif4.c diff | blob | history
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - secondary bootloader for legacy K1 SOCs: C6678/C6657.