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(parent: bd63345) | patch
DDR3 and PA SS PLL driver code update IBL_EXP_11_08
authorSandeep Paulraj <s-paulraj@ti.com>
Tue, 8 Nov 2011 19:55:14 +0000 (14:55 -0500)
committerSandeep Paulraj <s-paulraj@ti.com>
Tue, 8 Nov 2011 19:55:14 +0000 (14:55 -0500)
commit1f1152b9aeb94cf4663bbca37edf1c2750fb3de3
tree3e9e3dcb0ab51350b60db9774c90e398ae4e6edftree | snapshot (tar.xz tar.gz zip)
parentbd63345cbdb82a3c29266ea03778dff470edc073commit | diff
DDR3 and PA SS PLL driver code update

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/hw/plls/pll014phi/cfgpll.c diff | blob | history
src/hw/plls/pll014phi/cfgpll2.c diff | blob | history
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - secondary bootloader for legacy K1 SOCs: C6678/C6657.