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(parent: 86f576a) | patch
c66x: Move DDR3 PLL config
authorSandeep Paulraj <s-paulraj@ti.com>
Fri, 4 Nov 2011 17:34:22 +0000 (13:34 -0400)
committerSandeep Paulraj <s-paulraj@ti.com>
Fri, 4 Nov 2011 17:34:22 +0000 (13:34 -0400)
commit2677f90c3ba95697ceefc45b09dbd12294945f37
tree902d7bd225952cbd72437933126c12d87007e981tree | snapshot (tar.xz tar.gz zip)
parent86f576a422e8da5deffd1c62b375925eea7cd169commit | diff
c66x: Move DDR3 PLL config

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/device/c66x/c66xinit.c diff | blob | history
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - secondary bootloader for legacy K1 SOCs: C6678/C6657.