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raw | patch | inline | side by side (parent: 71dc296)
author | Sandeep Paulraj <s-paulraj@ti.com> | |
Wed, 2 Nov 2011 21:26:31 +0000 (17:26 -0400) | ||
committer | Sandeep Paulraj <s-paulraj@ti.com> | |
Wed, 2 Nov 2011 21:26:31 +0000 (17:26 -0400) |
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/hw/ddrs/emif4/emif4.c | patch | blob | history |
index d06a38e05b5eb48fba55c240e525d26c0f6380b1..5e31e1813e27b2c8eab458de44ed00c83775f3b6 100644 (file)
/* 1333 MHz data rate */
/***************** 2.2 DDR3 PLL Configuration ************/
DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
+ DDR3PLLCTL0 |= 0x00800000; // Set BYPASS = 1
DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
+
DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ
for (i = 0;i < 20;i++)
for (i = 0;i < 500;i++)
ddr3_wait(1000); //Wait for PLL lock
+ DDR3PLLCTL0 &= ~(0x00800000); // Set BYPASS = 0
+
/**************** 3.0 Leveling Register Configuration ********************/
/* Using partial automatic leveling due to errata */