author | Bill Mills <wmills@ti.com> | |
Mon, 9 May 2011 18:38:05 +0000 (14:38 -0400) | ||
committer | Bill Mills <wmills@ti.com> | |
Mon, 9 May 2011 18:38:05 +0000 (14:38 -0400) |
Conflicts:
doc/release_info.txt
src/hw/ddrs/emif4/emif4.c
src/ibl.h
src/make/setupenv.bat
src/make/setupenvMsys.sh
src/util/i2cConfig/i2cConfig.gel
Manual overrides
release.sh
src/driver/nand.c
src/make/Makefile
src/make/makestg1
src/make/makestg2
src/util/i2cConfig/i2cparam.c
src/util/i2cConfig/i2cConfig.gel
doc/release_info.txt
src/hw/ddrs/emif4/emif4.c
src/ibl.h
src/make/setupenv.bat
src/make/setupenvMsys.sh
src/util/i2cConfig/i2cConfig.gel
Manual overrides
release.sh
src/driver/nand.c
src/make/Makefile
src/make/makestg1
src/make/makestg2
src/util/i2cConfig/i2cparam.c
src/util/i2cConfig/i2cConfig.gel
1 | 2 | |||
---|---|---|---|---|
release.sh | patch | | diff1 | | diff2 | | blob | history |
src/driver/nand/nand.c | patch | | diff1 | | diff2 | | blob | history |
src/make/Makefile | patch | | diff1 | | diff2 | | blob | history |
src/make/makestg2 | patch | | diff1 | | diff2 | | blob | history |
src/util/i2cConfig/i2cConfig.gel | patch | | diff1 | | diff2 | | blob | history |
diff --cc release.sh
index 32b81714674744683f39baa47b3f46ab796a9971,63a59efbc7f60206eb5251daa78d234ab296a205..9e6961300dd8cd27a633edb2960c7e07d0424f31
--- 1/release.sh
--- 2/release.sh
+++ b/release.sh
#!/bin/sh
# Generate the source release tarballs
- export IBL_VERSION="1_0_0_3"
-export IBL_VERSION="1_0_0_2"
++export IBL_VERSION="1_0_0_4"
cd ../
if [ -f ibl_src_$IBL_VERSION.tgz ]; then rm ibl_src_$IBL_VERSION.tgz; fi
# Build c6678 EVM
pushd src/make
make clean
--make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51
++make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51
popd
cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6678/le/i2crom_0x51_c6678_le.dat
cp -f src/util/i2cWrite/i2cWrite_le.out ibl_bin_$IBL_VERSION/c6678/le/i2cWrite_c6678_le.out
cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6678/le/i2cparam_c6678_le.out
--
--# Build c6670 EVM
--pushd src/make
--make clean
--make evm_c6670_i2c ENDIAN=little I2C_BUS_ADDR=0x51
--popd
cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.dat
cp -f src/util/i2cWrite/i2cWrite_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cWrite_c6670_le.out
cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cparam_c6670_le.out
diff --cc src/driver/nand/nand.c
Simple merge
diff --cc src/make/Makefile
index 6885e3634630a7f4d9e15801cf5b1196acff5aa0,3a498fdc3c0660700d7a1b7b9f0f2708ee4f8db8..2ac143182cf2162139321bba244522f40bb0bf54
--- 1/src/make/Makefile
--- 2/src/make/Makefile
+++ b/src/make/Makefile
evm_c6608:
make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
- # The 6678 EVM SPI/NOR Boot
- EVM_6678_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
-
- evm_c6678_spi:
- make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+ # The 667x EVM SPI/NOR Boot
+ EVM_667x_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
- evm_c6678_i2c:
- make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+ evm_c667x_spi:
+ make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
- evm_c6670_i2c:
- make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+ evm_c667x_i2c:
- make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no INTERNAL_UTILS=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
++ make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
test_c661x:
make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c661x
diff --cc src/make/makestg2
index 0f85c1660abe862f20ab40605cb5fbc07bd8b091,760329ade53ce185497dbfd50338c060f5bbc1eb..23062d5502c8cd6cbcf397379a719342f3a3a4d7
--- 1/src/make/makestg2
--- 2/src/make/makestg2
+++ b/src/make/makestg2
endif
endif
--ifeq ($(HAS_SPI),0)
-- SPI_CFG=
--endif
i2crom:
$(CC) -ppo -I../cfg/$(TARGET) $(I2C_DEFS) ibl_$(TARGET)/$@.map.pre
diff --cc src/util/i2cConfig/i2cConfig.gel
index fba6a7d8ecfa243fab5d688f1e1ff66280640e4b,10ff08df76ab2f3d51977bda0e9daa3712776d32..a7ce68b0c12e0c046340e3a490c2580c756358f0
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress = 0;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
++ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
++ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
- ibl.bootModes[0].u.norBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob.sizeBytes = 0x80000; /* 512 KB */
- ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
++ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
++ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
++ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
+
- ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
-
++ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
- ibl.bootModes[1].port = ibl_PORT_SWITCH_ALL;
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
- ibl.bootModes[1].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
- ibl.bootModes[1].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr, 192,168,1,100);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp, 192,168,1,101);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
/* Use the e-fuse value */
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
-
-
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0] = 'a';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1] = 'p';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2] = 'p';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3] = '.';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4] = 'o';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5] = 'u';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6] = 't';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
-
- ibl.bootModes[1].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
-
- ibl.chkSum = 0;
- }
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
- ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* Image size (10 MB) */
- ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
++ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- hotmenu setConfig_c6678_emac()
- {
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY+1;
- ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
- }
-
- hotmenu setConfig_c6678_nand()
- {
- /* Nand boot is higher priority */
- ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NAND;
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
- ibl.bootModes[0].port = 0;
-
- ibl.bootModes[0].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.nandBoot.bootAddress = 0;
- ibl.bootModes[0].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
- ibl.bootModes[0].u.nandBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.nandBoot.blob.sizeBytes = 0x80000; /* 512 KB */
- ibl.bootModes[0].u.nandBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
-
- ibl.bootModes[0].u.nandBoot.nandInfo.busWidthBits = 8;
- ibl.bootModes[0].u.nandBoot.nandInfo.pageSizeBytes = 512;
- ibl.bootModes[0].u.nandBoot.nandInfo.pageEccBytes = 16;
- ibl.bootModes[0].u.nandBoot.nandInfo.pagesPerBlock = 32;
- ibl.bootModes[0].u.nandBoot.nandInfo.totalBlocks = 4096;
-
- ibl.bootModes[0].u.nandBoot.nandInfo.addressBytes = 4;
- ibl.bootModes[0].u.nandBoot.nandInfo.lsbFirst = TRUE;
- ibl.bootModes[0].u.nandBoot.nandInfo.blockOffset = 14;
- ibl.bootModes[0].u.nandBoot.nandInfo.pageOffset = 9;
- ibl.bootModes[0].u.nandBoot.nandInfo.columnOffset = 0;
-
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[4] = 6;
- ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[5] = 7;
-
- ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
- ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xffff;
-
- ibl.bootModes[0].u.nandBoot.nandInfo.resetCommand = 0xff;
- ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPre = 0;
- ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPost = 0;
- ibl.bootModes[0].u.nandBoot.nandInfo.postCommand = FALSE;
+ ibl.chkSum = 0;
}
menuitem "EVM c6670 IBL";
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress = 0;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
++ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
++ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
- ibl.bootModes[0].u.norBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[0].u.norBoot.blob.sizeBytes = 0x80000; /* 512 KB */
- ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
-
- ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
- ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
- ibl.bootModes[1].port = ibl_PORT_SWITCH_ALL;
- ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
++ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
- ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
++ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
++ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
- ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x90000000; /* Image 1 load start address in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in LE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x90000000; /* Image 1 load start address in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
- ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000; /* Image 1 branch address after loading in BE mode */
-
++ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
- ibl.bootModes[1].u.ethBoot.doBootp = FALSE;
- ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
- ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
- ibl.bootModes[1].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr, 192,168,1,100);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp, 192,168,1,101);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
- SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
/* Use the e-fuse value */
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
- ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
-
-
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0] = 'a';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1] = 'p';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2] = 'p';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3] = '.';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4] = 'o';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5] = 'u';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6] = 't';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
- ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
-
- ibl.bootModes[1].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
-
- ibl.chkSum = 0;
- }
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
- ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
- ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* Image size (10 MB) */
- ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
++ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
++ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
++ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- hotmenu setConfig_c6670_emac()
- {
- ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY+1;
- ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.chkSum = 0;
}
+