Merge branch 'nysh_multi_boot'
authorBill Mills <wmills@ti.com>
Mon, 9 May 2011 18:38:05 +0000 (14:38 -0400)
committerBill Mills <wmills@ti.com>
Mon, 9 May 2011 18:38:05 +0000 (14:38 -0400)
Conflicts:
doc/release_info.txt
src/hw/ddrs/emif4/emif4.c
src/ibl.h
src/make/setupenv.bat
src/make/setupenvMsys.sh
src/util/i2cConfig/i2cConfig.gel

Manual overrides
release.sh
src/driver/nand.c
src/make/Makefile
src/make/makestg1
src/make/makestg2
src/util/i2cConfig/i2cparam.c
src/util/i2cConfig/i2cConfig.gel

24 files changed:
release.sh
src/device/c661x/c661xinit.c
src/driver/nand/nand.c
src/driver/nor/nor.c
src/ethboot/ethboot.c
src/hw/ddrs/emif4/emif4.c
src/hw/emif25/emif25.c
src/hw/emif25/emif25_loc.h
src/hw/nands/emif25/nandemif25.c
src/hw/spi/spi.c
src/hw/spi/spi_api.h
src/hw/spi/spi_loc.h
src/ibl.h
src/interp/elf/dlw_client.c
src/main/iblStage.h
src/main/iblinit.c
src/main/iblmain.c
src/make/Makefile
src/make/ibl_c661x/ibl_common.inc
src/make/makestg2
src/make/setupenv.bat
src/nandboot/nandboot.c
src/norboot/norboot.c
src/util/i2cConfig/i2cConfig.gel

index 32b81714674744683f39baa47b3f46ab796a9971..9e6961300dd8cd27a633edb2960c7e07d0424f31 100755 (executable)
@@ -1,6 +1,6 @@
 #!/bin/sh
 # Generate the source release tarballs
-export IBL_VERSION="1_0_0_3"
+export IBL_VERSION="1_0_0_4"
 cd ../
 if [ -f ibl_src_$IBL_VERSION.tgz ]; then rm ibl_src_$IBL_VERSION.tgz; fi
 
@@ -121,17 +121,11 @@ cp -f src/util/i2cConfig/i2cparam_c6457_be.out   ibl_bin_$IBL_VERSION/c6457/be/
 # Build c6678 EVM 
 pushd src/make
 make clean
-make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
 popd
 cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6678/le/i2crom_0x51_c6678_le.dat
 cp -f src/util/i2cWrite/i2cWrite_le.out   ibl_bin_$IBL_VERSION/c6678/le/i2cWrite_c6678_le.out
 cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6678/le/i2cparam_c6678_le.out
-
-# Build c6670 EVM 
-pushd src/make
-make clean
-make evm_c6670_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
-popd
 cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.dat
 cp -f src/util/i2cWrite/i2cWrite_le.out   ibl_bin_$IBL_VERSION/c6670/le/i2cWrite_c6670_le.out
 cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cparam_c6670_le.out
index 28036955a53499013871392019e1b29838b78b8b..03dbcd1deb228d1f4ccb0d1e740230e2ca3da009 100644 (file)
@@ -235,6 +235,11 @@ void iblEnterRom ()
         exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
         (*exit)();        
     }
+    else
+    {
+        /* Update the DEVSTAT register for the actual boot configuration */
+        DEVICE_REG32_W (DEVICE_REG_DEVSTAT, ((bm_hi << 8) | bm_lo));
+    }
 }
 
 #if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
index a35ac042472a6fa5a4b9f42231905ee69591c787..1261694f9eb4eb007bdb647305f834b5a061c16f 100644 (file)
@@ -185,7 +185,7 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
 
     /* Initialize the control info */
     iblMemset (&nandmcb, 0, sizeof(nandmcb));
-    iblMemcpy (&nandmcb.devInfo, &ibln->nandInfo, sizeof(iblNand_t));
+    iblMemcpy (&nandmcb.devInfo, &ibln->nandInfo, sizeof(nandDevInfo_t));
 
     nandmcb.page             = NULL;
     nandmcb.logicalToPhysMap = NULL;
@@ -260,8 +260,8 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
             {
                 ret = (*nandmcb.nand_if->nct_driverReadBytes)(i, 
                     j, 
-                    0, //nandmcb.devInfo.pageSizeBytes, 
-                    nandmcb.devInfo.pageSizeBytes+nandmcb.devInfo.pageEccBytes,//nandmcb.devInfo.pageEccBytes, 
+                    nandmcb.devInfo.pageSizeBytes, 
+                    nandmcb.devInfo.pageEccBytes, 
                     nandmcb.page);
                 if (ret < 0)
                 {
@@ -269,8 +269,7 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
                     return (-1);
                 }
                 
-                //if (nandmcb.page[nandmcb.devInfo.badBlkMarkIdx[j]] != 0xff)
-                if (nandmcb.page[nandmcb.devInfo.pageSizeBytes+nandmcb.devInfo.badBlkMarkIdx[j]] != 0xff)
+                if (nandmcb.page[nandmcb.devInfo.badBlkMarkIdx[j]] != 0xff)
                 {
                     badBlock = TRUE;
                     break;
@@ -306,8 +305,8 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
     nandmcb.fpos                = -1;      /* Force a read on the first seek */
     nandmcb.currentLogicalBlock = 0xffffffff;
     nandmcb.currentPage         = 0xffffffff;
-    nand_seek (0, 0);
 
+    nand_seek (ibln->bootAddress[iblEndianIdx][iblImageIdx], 0);
             
     return (0);
 
index 6eafe4cd0fd83624f599b680c833e5661ce00a75..9f0f6c391517237db0b8921390424cb654573547 100644 (file)
@@ -92,7 +92,7 @@ Int32 nor_open (void *ptr_driver, void (*asyncComplete)(void *))
 {
     iblNor_t *ibln = (iblNor_t *)ptr_driver;
 
-    normcb.startPos = normcb.fpos = ibln->bootAddress;
+    normcb.startPos = normcb.fpos = ibln->bootAddress[iblEndianIdx][iblImageIdx];
     normcb.nor_if   = deviceGetNorCtbl (ibln->interface);
 
     return (0);
index 56c480e5789fd16ead74da3e50fec6cd6c3ede80..163a411b1133e81a85d9e0e3a6e49eb0954fff14 100644 (file)
@@ -131,7 +131,7 @@ void iblEthBoot (Int32 eIdx)
     /* SGMII configuration. If sgmii is not present this statement is defined
      * to void in target.h */
     for (n = 0; n < ibl_N_ETH_PORTS; n++)  {
-        if (ibl.sgmiiConfig[eIdx].configure == TRUE)
+        if (ibl.sgmiiConfig[n].configure == TRUE)
             hwSgmiiConfig (n, &ibl.sgmiiConfig[n]);
     }
 
index 39c1904fd8f323558237a550ec78faa5db1596c2..ba0a63cc7ce2c9593475b480c8e2e149fcd20594 100644 (file)
@@ -33,6 +33,7 @@
 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
+#define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
 
 #define DATA0_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262043C))
 #define DATA1_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620440))
 #define DATA7_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620458))
 #define DATA8_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262045C))
 
+#define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
+#define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
+#define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
+#define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
+#define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
+#define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
+#define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
+#define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
+#define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
+
 #define RDWR_INIT_RATIO_0      (*(volatile unsigned int*)(0x0262040C))
 #define RDWR_INIT_RATIO_1      (*(volatile unsigned int*)(0x02620410))
 #define RDWR_INIT_RATIO_2      (*(volatile unsigned int*)(0x02620414))
@@ -54,6 +65,7 @@
 #define RDWR_INIT_RATIO_7      (*(volatile unsigned int*)(0x02620428))
 #define RDWR_INIT_RATIO_8      (*(volatile unsigned int*)(0x0262042C))
 
+
 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
 #define WR_DATA_SLAVE_RATIO 0xE9
 #define FIFO_WE_SLAVE_RATIO 0x106
 
+
+static void ddr3_wait (uint32 del)
+{
+    volatile unsigned int i;
+
+    for (i = 0; i < del; i++);
+
+}
+
 /*************************************************************************************************
  * FUNCTION PUROPSE: Initial EMIF4 setup
  *************************************************************************************************
 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
 {
     UINT32 v, i;
-
-#if 0
-    /* If the config registers or refresh control registers are being written
-     * disable the initialization sequence until they are all setup */
-    if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
-
-        v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
-        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-    }
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
-
-    /* Allow the configuration to occur */
-    v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
-    EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
-    DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
-
-    v = cfg->sdRamRefreshCtl;
-    EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
-    DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-#endif
-
+    
     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
-
-    /*KICK0 = 0x83E70B13;
-    KICK1 = 0x95A4F1E0;*/
-
+    
     if (v == DEVICE_C6618_JTAG_ID_VAL)
     {
+#if 0
+        /* C6678 Old 1066 configuration */
         DDR3PLLCTL0 = 0x100807C1;
         
         DDR_SDTIM1   = 0x0CCF369B;
@@ -225,9 +156,137 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
         DDR_SDTIM1; //Read MMR to ensure full leveling is complete
         
         DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
+#endif
+#if 1
+        /* C6678 1333 MHz data rate */
+        /***************** 2.2 DDR3 PLL Configuration ************/
+        DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
+        DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
+        DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ
+        ddr3_wait(1000);               //Wait for reset to complete
+        DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
+        ddr3_wait(1000);              //Wait for PLL lock
+        
+        /***************** 2.3 Basic Controller and DRAM configuration ************/
+        DDR_SDRFC    = 0x80005162;    // inhibit configuration 
+        
+        DDR_SDTIM1   = 0x1113783C;
+        DDR_SDTIM2   = 0x304F7FE3;
+        DDR_SDTIM3   = 0x559F849F;
+        
+        DDR_DDRPHYC  = 0x0010010F;
+        
+        DDR_ZQCFG    = 0x70073214;
+        
+        DDR_PMCTL    = 0x0;
+        
+        DDR_SDRFC    = 0x00005162;    // enable configuration
+        DDR_SDCFG    = 0x63222A32;    // last config write \96 DRAM init occurs
+        
+        ddr3_wait(1000);            //Wait for HW init to complete
+        DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
+        
+        /**************** 3.0 Leveling Register Configuration ********************/
+        /* Using partial automatic leveling due to errata */
+        
+        /**************** 3.2 Invert Clock Out ********************/
+        DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
+        DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
+        DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
+        DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
+        
+        
+        /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+        DATA0_WRLVL_INIT_RATIO = 0x20;
+        DATA1_WRLVL_INIT_RATIO = 0x24;
+        DATA2_WRLVL_INIT_RATIO = 0x3A;
+        DATA3_WRLVL_INIT_RATIO = 0x38;
+        DATA4_WRLVL_INIT_RATIO = 0x51;
+        DATA5_WRLVL_INIT_RATIO = 0x5E;
+        DATA6_WRLVL_INIT_RATIO = 0x5E;
+        DATA7_WRLVL_INIT_RATIO = 0x5E;
+        DATA8_WRLVL_INIT_RATIO = 0x44;
+        
+        DATA0_GTLVL_INIT_RATIO = 0xA1;
+        DATA1_GTLVL_INIT_RATIO = 0x9E;
+        DATA2_GTLVL_INIT_RATIO = 0xA7;
+        DATA3_GTLVL_INIT_RATIO = 0xA9;
+        DATA4_GTLVL_INIT_RATIO = 0xCA;
+        DATA5_GTLVL_INIT_RATIO = 0xBE;
+        DATA6_GTLVL_INIT_RATIO = 0xDD;
+        DATA7_GTLVL_INIT_RATIO = 0xDD;
+        DATA8_GTLVL_INIT_RATIO = 0xBA;
+        
+        DDR3_CONFIG_REG_23 |= 0x00000200;
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
+        DDR_RDWR_LVL_CTRL = 0x80000000;
+#endif
+        
+#if 0
+        /* C6678 New 1066 rate */
+        /***************** 2.2 DDR3 PLL Configuration ************/
+        DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
+        DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
+        DDR3PLLCTL0 = 0x0F0807C1;       //Configure CLKR, CLKF, CLKOD, BWADJ
+        ddr3_wait(1000);              //Wait for reset to complete
+        DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
+        ddr3_wait(1000);
+        
+        /***************** 2.3 Basic Controller and DRAM configuration ************/
+        DDR_SDRFC    = 0x8000411B;    // inhibit configuration 
+        DDR_SDTIM1   = 0x0CCF36B3;
+        DDR_SDTIM2   = 0x303F7FDA;
+        DDR_SDTIM3   = 0x559F83AF;
+        
+        DDR_DDRPHYC  = 0x0010010A;
+        DDR_ZQCFG    = 0x70073214;
+        
+        //DDR_PMCTL    = 0x0;
+        DDR_SDRFC    = 0x0000411B;    // enable configuration
+        DDR_SDCFG    = 0x63211A32;    // last config write \96 DRAM init occurs
+        
+        ddr3_wait(1000);             //Wait for HW init to complete
+        
+        DDR_SDRFC = 0x00001040;       //Refresh rate = (7.8*666MHz]
+        
+        /**************** 3.0 Leveling Register Configuration ********************/
+        /* Using partial automatic leveling due to errata */
+        
+        /**************** 3.2 Invert Clock Out ********************/
+        DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
+        DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
+        DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
+        DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
+        
+        /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+        DATA0_WRLVL_INIT_RATIO = 0x19;//0x4C;
+        DATA1_WRLVL_INIT_RATIO = 0x1C;//0x4C;
+        DATA2_WRLVL_INIT_RATIO = 0x2F;//0x4C;
+        DATA3_WRLVL_INIT_RATIO = 0x2D;//0x42;
+        DATA4_WRLVL_INIT_RATIO = 0x42;//0x2D;
+        DATA5_WRLVL_INIT_RATIO = 0x4C;//0x2F;
+        DATA6_WRLVL_INIT_RATIO = 0x4C;//0x1C;
+        DATA7_WRLVL_INIT_RATIO = 0x4C;//0x19;
+        DATA8_WRLVL_INIT_RATIO = 0x37;
+        
+        DATA0_GTLVL_INIT_RATIO = 0x8D;//0xBC;
+        DATA1_GTLVL_INIT_RATIO = 0x8A;//0xBC;
+        DATA2_GTLVL_INIT_RATIO = 0x91;//0xA4;
+        DATA3_GTLVL_INIT_RATIO = 0x93;//0xAE;
+        DATA4_GTLVL_INIT_RATIO = 0xAE;//0x93;
+        DATA5_GTLVL_INIT_RATIO = 0xA4;//0x91;
+        DATA6_GTLVL_INIT_RATIO = 0xBC;//0x8A;
+        DATA7_GTLVL_INIT_RATIO = 0xBC;//0x8D;
+        DATA8_GTLVL_INIT_RATIO = 0xA1;
+        
+        DDR3_CONFIG_REG_23 |= 0x00000200;
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
+        DDR_RDWR_LVL_CTRL = 0x80000000;
+#endif
     }
-    else
+    else if (v == DEVICE_C6616_JTAG_ID_VAL)
     {
+        /* C6670 800 M rate */
         DDR3PLLCTL1 |= 0x00000040;    //Set ENSAT = 1
         DDR3PLLCTL1 |= 0x00002000;    //Set RESET bit before programming DDR3PLLCTL0
         DDR3PLLCTL0 = 0x02000140;
@@ -259,7 +318,97 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
         
         DDR_SDRFC    = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
     }
-
+    else
+    {
+        /* C64x configuration */
+        /* If the config registers or refresh control registers are being written
+         * disable the initialization sequence until they are all setup */
+        if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
+            
+            v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+            EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+        }
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
+        
+        /* Allow the configuration to occur */
+        v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
+        
+        v = cfg->sdRamRefreshCtl;
+        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+    }
+    
     return (0);
 
 } /* hwEmif4p0Enable */
index 754136cddd2d5d39d88309af6fb895380a590db2..765d6aa6bfc1ec4d8673cccedd543be0122353a0 100644 (file)
@@ -70,7 +70,7 @@ Int32 hwEmif25Init (int32 cs, int32 busWidth, bool wait, bool nand)
         return (EMIF25_INVALID_BUS_WIDTH);
     
     /* Setup the bus width. The macro uses the actual chip select value, 2-5 */
-    reg = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_ASYNC_CFG_REG(cs));
+    reg = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_ASYNC_CFG_REG(cs-2));
     reg = EMIF25_SET_ASYNC_WID(reg, v);
 
     /* Enable extended wait if requested */
@@ -81,7 +81,7 @@ Int32 hwEmif25Init (int32 cs, int32 busWidth, bool wait, bool nand)
 
     reg = EMIF25_SET_ASYNC_WAIT(reg, v);
 
-    DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_ASYNC_CFG_REG(cs), reg);
+    DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_ASYNC_CFG_REG(cs-2), reg);
 
     /* Nand enable */
     if (nand)
index 2640b421ae312d73a8b3413e377007732f4a5d0c..b86ca26eee2a79a4e7246b893612029a7c7ec72d 100644 (file)
 /* Register offsets */
 #define EMIF25_ASYNC_CFG_REG(x)       (0x10 + (x)*4)
 #define EMIF25_FLASH_CTL_REG          0x60
+#define EMIF25_FLASH_STATUS_REG       0x64
+#define EMIF25_FLASH_ECC_LOAD_REG     0xbc
 #define EMIF25_FLASH_ECC_REG(x)       (0xc0 + (x)*4)
+#define EMIF25_FLASH_ECC_LOAD_REG     0xbc
+#define EMIF25_FLASH_ERR_ADDR_REG(x)  (0xd0 + (x)*4)
+#define EMIF25_FLASH_ERR_VALUE_REG(x) (0xd8 + (x)*4)
 
 /* Setting the bus width in the async config register */
 #define EMIF25_SET_ASYNC_WID(x,v)     BOOT_SET_BITFIELD((x),(v),1,0)
@@ -50,7 +55,5 @@
 /* Setting the nand enable/disable in the flash control register */
 #define EMIF25_SET_FLASH_CTL_NAND_ENABLE(x,v,cs)   BOOT_SET_BITFIELD((x),(v),((cs)-2),((cs)-2))
 
-
-
-
 #endif /* _EMIF25_LOCK_H */
+
index fdcf9683ec4c1151cde827191ab7cf9724f4aec5..742f6aa603c14f513ff362dabf36068de8e9f41e 100644 (file)
@@ -79,6 +79,136 @@ nandCmdSet
     DEVICE_REG8_W (memBase + NAND_CMD_OFFSET, cmd);
 }
 
+
+/* Read raw ECC code after writing to NAND. */
+static void
+NandRead4bitECC
+(
+    Uint32    *code
+)
+{
+    Uint32    mask = 0x03ff03ff;
+
+    code[0] = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(0)) & mask;
+    code[1] = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(1)) & mask;
+    code[2] = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(2)) & mask;
+    code[3] = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(3)) & mask;
+}
+
+
+/* Correct up to 4 bits in data we just read, using state left in the
+* hardware plus the ecc_code computed when it was first written.
+*/
+static Int32
+NandCorrect4bitECC
+(
+    Uint8     *data,
+    Uint8     *ecc_code
+)
+{
+    Int32     i;
+    Uint16    ecc10[8];
+    Uint16    *ecc16;
+    Uint32    syndrome[4];
+    Uint32    num_errors, corrected, v;
+
+    /* All bytes 0xff?  It's an erased page; ignore its ECC. */
+    for (i = 0; i < 10; i++) {
+        if (ecc_code[i] != 0xff)
+            goto compare;
+    }
+    return 0;
+
+compare:
+/* Unpack ten bytes into eight 10 bit values.  We know we're
+* little-endian, and use type punning for less shifting/masking.
+    */
+    ecc16 = (Uint16 *)ecc_code;
+
+    ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
+    ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
+    ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
+    ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
+    ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
+    ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
+    ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
+    ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
+
+    /* Tell ECC controller about the expected ECC codes. */
+    for (i = 7; i >= 0; i--)
+    {
+        DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_LOAD_REG, ecc10[i]);
+    }
+
+    /* Allow time for syndrome calculation ... then read it.
+     * A syndrome of all zeroes 0 means no detected errors.
+     */
+    v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_STATUS_REG);
+    NandRead4bitECC(syndrome);
+    if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
+        return 0;
+
+   /*
+    * Clear any previous address calculation by doing a dummy read of an
+    * error address register.
+    */
+    v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_ADDR_REG(0));
+
+    /* Start address calculation, and wait for it to complete.
+    * We _could_ start reading more data while this is working,
+    * to speed up the overall page read.
+    */
+    v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG);
+    DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG, v | (1<<13));
+    for (;;) {
+        Uint32    fsr = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_STATUS_REG);
+
+        switch ((fsr >> 8) & 0x0f) {
+        case 0:     /* no error, should not happen */
+            v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_VALUE_REG(0));
+            return 0;
+        case 1:     /* five or more errors detected */
+            v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_VALUE_REG(0));
+            return -1;
+        case 2:     /* error addresses computed */
+        case 3:
+            num_errors = 1 + ((fsr >> 16) & 0x03);
+            goto correct;
+        default:    /* still working on it */
+            chipDelay32 (NAND_DELAY);
+            continue;
+        }
+    }
+
+correct:
+    /* correct each error */
+    for (i = 0, corrected = 0; i < num_errors; i++) {
+        int error_address, error_value;
+
+        if (i > 1) {
+            error_address = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_ADDR_REG(1));
+            error_value = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_VALUE_REG(1));
+        } else {
+            error_address = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_ADDR_REG(0));
+            error_value = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ERR_VALUE_REG(0));
+        }
+
+        if (i & 1) {
+            error_address >>= 16;
+            error_value >>= 16;
+        }
+        error_address &= 0x3ff;
+        error_address = (512 + 7) - error_address;
+
+        if (error_address < 512) {
+            data[error_address] ^= error_value;
+            corrected++;
+        }
+    }
+
+    return corrected;
+}
+
 void 
 nandReadDataBytes
 (
@@ -131,7 +261,16 @@ Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32
 
     addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset) | ((byte & 0xff) << hwDevInfo->columnOffset);   
 
-    cmd = hwDevInfo->readCommandPre;
+    if (byte < hwDevInfo->pageSizeBytes) 
+    {
+        /* Read page data */
+        cmd = hwDevInfo->readCommandPre;
+    }
+    else
+    {
+        /* Read spare area data */
+        cmd = 0x50;
+    }
     nandCmdSet(cmd); // First cycle send 0
 
     /* 4 address cycles */
@@ -155,9 +294,9 @@ Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data)
 {
     Int32   i, j, nSegs;
     Int32   addr;
-    Uint8  *blockp, *pSpareArea;
-    Uint8   eccCompute[3];
-    Uint8   eccFlash[3];
+    Uint8  *pSpareArea;
+    Uint8   eccFlash[ibl_N_ECC_BYTES];
+    Uint32  v;
 
     addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset);   
 
@@ -172,28 +311,31 @@ Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data)
 
     chipDelay32 (NAND_DELAY);
 
-    /* Read the data */
-    nandReadDataBytes(hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes, data);
-    pSpareArea = &data[hwDevInfo->pageSizeBytes];
-     
-    /* Break the page into segments of 256 bytes, each with its own ECC */
-    nSegs = hwDevInfo->pageSizeBytes >> 8;
+    /* Start 4-bit ECC calculation */
+    v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG);
+    DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG, v | (1<<12));
 
-    for (i = 0; i < nSegs; i++)  {
-        
-        blockp = &data[i << 8];
+    /* Read the page data */
+    nandReadDataBytes(hwDevInfo->pageSizeBytes, data);
 
-        /* Format the ecc values to match what the software is looking for */
-        for (j = 0; j < 3; j++)
-        {
-            eccFlash[j] = pSpareArea[hwDevInfo->eccBytesIdx[i*3+j]];
-        }
+   /* After a read, terminate ECC calculation by a dummy read
+    * of some 4-bit ECC register.
+    */
+    v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(0));
 
-        eccComputeECC(blockp, eccCompute);
-        if (eccCorrectData (blockp, eccFlash, eccCompute))
-        {
-            return (NAND_ECC_FAILURE);
-        }
+    /* Read the spare area data */
+    pSpareArea = &data[hwDevInfo->pageSizeBytes];
+    nandReadDataBytes(hwDevInfo->pageEccBytes, pSpareArea);
+    
+    /* Get the ECC bytes from the spare area data */
+    for (i = 0; i < ibl_N_ECC_BYTES; i++)
+    {
+        eccFlash[i] = pSpareArea[hwDevInfo->eccBytesIdx[i]];
+    }
+    
+    if (NandCorrect4bitECC(data, eccFlash) < 0)
+    {
+        return (NAND_ECC_FAILURE);
     }
 
     return (0);
index d9a351425ac37f8c736ac0a6b6e0d6d1730009e4..6702858191204917a2eec672ddd5d26e4e7c56cb 100644 (file)
@@ -114,7 +114,7 @@ SINT16 hwSpiConfig (spiConfig_t *cfg)
  *************************************************************************************************
  * DESCRIPTION: A bi-directional transfer is done
  *************************************************************************************************/
-SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate)
+SINT16 hw_spi_xfer (UINT32 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate)
 {
     UINT32 v;
     UINT32 i;
@@ -227,7 +227,7 @@ SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *c
  *************************************************************************************************
  * DESCRIPTION: A single data block of a fixed size is read
  *************************************************************************************************/
-SINT16 hwSpiRead (UINT32 addr, UINT16 sizeBytes, UINT8 *data)
+SINT16 hwSpiRead (UINT32 addr, UINT32 sizeBytes, UINT8 *data)
 {
     UINT32 n;
     UINT8  command[4];
index 247931bb435818a4e2911231b5e09867bfb2700e..abf82bec4276b150e22fcf788c9102864ed4b5c5 100644 (file)
@@ -20,7 +20,7 @@ typedef struct spiConfig_s  {
 } spiConfig_t;
 
 SINT16 hwSpiConfig (spiConfig_t *spiCfg);
-SINT16 hwSpiRead (UINT32 addr, UINT16 sizeBytes, UINT8 *data);
+SINT16 hwSpiRead (UINT32 addr, UINT32 sizeBytes, UINT8 *data);
 void hwSpiEnableXfer (UINT32 port);
 void hwSpiDisableXfer (UINT32 port);
 
index 679dd21cfd71dabc88e5fa50d1d28ab1bb25e1a0..8222260e146eade8006bdb50b4df97deb3d97cd3 100644 (file)
@@ -57,6 +57,6 @@
 #define SPI_COMMAND_WRITE_ENABLE    0x06
 #define SPI_COMMAND_ERASE_SECTOR    0x20
 
-SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate);
+SINT16 hw_spi_xfer (UINT32 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate);
 
 #endif /* _SPI_LOC_H */
index 6ee3d10e148fa218fe769079ff596bee8e5b1a22..73da665144ab779dea67f1ad33c000340761727c 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
@@ -1,34 +1,34 @@
 /*
  *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 
- * 
- * 
- *  Redistribution and use in source and binary forms, with or without 
- *  modification, are permitted provided that the following conditions 
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
  *  are met:
  *
- *    Redistributions of source code must retain the above copyright 
+ *    Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  *
  *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the   
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
  *    distribution.
  *
  *    Neither the name of Texas Instruments Incorporated nor the names of
  *    its contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
  *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
 */
@@ -51,7 +51,7 @@
  *
  *  @brief
  *      This file defines the configuration and control of the IBL
- *  
+ *
  *
  ********************************************************************************************************/
 #ifndef IBL_H
@@ -65,9 +65,9 @@
 
 /**
  * @brief
- *  The version number, 1.0.0.3
+ *  The version number, 1.0.0.4
  */
-#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,3)
+#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,4)
 
 
 /**
@@ -78,7 +78,7 @@
  *
  *  @def ibl_BOOT_MODE_TFTP */
  #define ibl_BOOT_MODE_TFTP     10      /* Boot through a tftp interface */
+
  /* @def ibl_BOOT_MODE_NAND */
 #define  ibl_BOOT_MODE_NAND     11      /* Boot through a nand interface */
 
@@ -95,9 +95,8 @@
  *      Define the number of different boot modes which can be configured for
  *      a single execution of the IBL.
  */
-#define ibl_N_BOOT_MODES        2
+#define ibl_N_BOOT_MODES        3
 
 /* Information used to make generate a bootp request */
 /**
  * @brief
@@ -110,18 +109,18 @@ typedef struct iblBootp_s
 {
     uint8   hwAddress[6]; /**< The hardware (mac) address of this device. If set to 0
                                the ibl will values from e-fuse */
-    
+
     uint8   ipDest[4];    /**< The IP address of this device. This is typically set
                                to IP broadcast */
-    
+
 } iblBootp_t;
 
 
 /**
  * @brief
- *   This structure contains information used for tftp boot. 
+ *   This structure contains information used for tftp boot.
  *
- * @details These fields are typically filled in by the bootp packet, but 
+ * @details These fields are typically filled in by the bootp packet, but
  *          can be provided if bootp will not be used.
  */
 typedef struct iblEthBootInfo_s
@@ -131,17 +130,17 @@ typedef struct iblEthBootInfo_s
     uint8   gatewayIp[4];   /**< The IP address of the gateway */
     uint8   netmask[4];     /**< The IP netmask */
     uint8   hwAddress[6];   /**< The hardware (mac) address of this device */
-    char8   fileName[128];  /**< The file name to load */
+    char8   fileName[64];  /**< The file name to load */
 
 } iblEthBootInfo_t;
-    
-    
+
+
 /**
  * @def ibl_ETH_PORT_FROM_RBL
  */
-#define ibl_ETH_PORT_FROM_RBL   -1  /**< The ethernet port used is the same one used 
+#define ibl_ETH_PORT_FROM_RBL   -1  /**< The ethernet port used is the same one used
                                          during the ROM boot load process. */
-                                         
+
 /**
  *  @def ibl_PORT_SWITCH_ALL
  */
@@ -154,7 +153,7 @@ typedef struct iblEthBootInfo_s
  *
  * @ingroup iblBootFormats
  * @{
- */ 
+ */
 #define ibl_BOOT_FORMAT_AUTO    0   /**< Auto determine the boot format from the data */
 #define ibl_BOOT_FORMAT_NAME    1   /**< Determines the boot format based on file name (bootp/tftp only) */
 #define ibl_BOOT_FORMAT_BIS     2   /**< Boot TI AIS format */
@@ -164,7 +163,7 @@ typedef struct iblEthBootInfo_s
 #define ibl_BOOT_FORMAT_BTBL    6   /**< Boot a TI boot table file */
 
 /* @} */
+
 /**
  * @defgroup iblPeriphPriority  Defines the boot sequence
  *
@@ -184,7 +183,7 @@ typedef struct iblEthBootInfo_s
  */
 #define ibl_DEVICE_NOBOOT       20  /**< Indicates that the device is not to be used for boot */
 
-/* @} */  
+/* @} */
 
 
 /**
@@ -201,7 +200,7 @@ typedef struct iblEmif3p1_s
     uint32 sdtim1;          /**< DDR timing register 1 */
     uint32 sdtim2;          /**< DDR timing register 2 */
     uint32 dmcctl;          /**< CAS match timing */
-    
+
 } iblEmif3p1_t;
 
 
@@ -239,7 +238,7 @@ typedef struct iblEmif4p0_s
     uint32  eccRange1;                  /**< ECC Address Range 1 Register */
     uint32  eccRange2;                  /**< ECC Address Range 2 Register */
     uint32  rdWrtExcThresh;             /**< Read Write Execution Threshold Register */
-   
+
 } iblEmif4p0_t;
 
 
@@ -323,10 +322,10 @@ typedef struct iblEmif4p0_s
 
 /** @def ibl_BOOT_EMIF4_ENABLE_ALL */
 #define  ibl_BOOT_EMIF4_ENABLE_ALL                    0x007fffff
-    
-/* @} */  
-    
-    
+
+/* @} */
+
+
 /**
  * @defgroup iblEmifType Defines the EMIF4 type on a device
  *
@@ -352,9 +351,9 @@ typedef struct iblEmif4p0_s
 typedef struct idblDdr_s
 {
     bool configDdr;                  /**<  Set to non-zero to enable EMIF configuration */
-    
+
     union  {
-    
+
         iblEmif3p1_t  emif3p1;       /**<  Configuration of devices with emif controller version 3.1 */
         iblEmif4p0_t  emif4p0;       /**<  Configuration of devices with emif controller version 4.0 */
     } uEmif;
@@ -393,12 +392,12 @@ typedef struct iblEth_s
                                      is used, if FALSE the one in the ethInfo field is used */
     bool     useBootpFileName;  /**< If TRUE then the file name received from the bootp server
                                      is used, if FALSE the one in the ethInfo field is used */
-    int32    bootFormat;        /**< The format of the boot data file. @ref iblBootFormats */                            
-    
+    int32    bootFormat;        /**< The format of the boot data file. @ref iblBootFormats */
+
     iblBinBlob_t blob;          /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
-    
+
     iblEthBootInfo_t  ethInfo;  /**< Low level ethernet information */
-    
+
 } iblEth_t;
 
 
@@ -417,7 +416,7 @@ typedef struct iblSgmii_s
     uint32  txConfig;           /**< Serdes Tx config                      */
     uint32  rxConfig;           /**< Serdes Rx config                      */
     uint32  auxConfig;          /**< Serdes Aux config                     */
-  
+
 } iblSgmii_t;
 
 
@@ -430,7 +429,7 @@ typedef struct iblSgmii_s
  *  @def ibl_N_MDIO_CFGS
  */
 #define ibl_N_MDIO_CFGS     16  /**< The maximum number of mdio configurations */
+
 
 /**
  * @brief
@@ -450,9 +449,9 @@ typedef struct iblMdio_s
 {
     int16  nMdioOps;         /**< The number of mdio writes to perform  */
     uint16 mdioClkDiv;       /**< The divide down of the mac clock which drives the mdio */
-    
+
     uint32 interDelay;       /**< The number of cpu cycles to wait between mdio writes */
-    
+
     uint32 mdio[ibl_N_MDIO_CFGS];   /* The MDIO transactions */
 
 } iblMdio_t;
@@ -460,14 +459,14 @@ typedef struct iblMdio_s
 /**
  *  @def ibl_N_ECC_BYTES
  */
-#define ibl_N_ECC_BYTES             6  /**< The number of ECC bytes to be computed for each page */
+#define ibl_N_ECC_BYTES             10  /**< The number of ECC bytes to be computed for each page */
 
 /**
  *  @def ibl_N_BAD_BLOCK_MARKER
  */
 #define ibl_N_BAD_BLOCK_PAGE      2  /**< The number of pages in each block that has the bad block marker */
 
-/** 
+/**
  *  @brief
  *      This structure defines the physical parameters of the NAND device
  */
@@ -478,26 +477,39 @@ typedef struct nandDevInfo_s
     uint32  pageEccBytes;       /**< Number of ecc bytes in each page */
     uint32  pagesPerBlock;      /**< The number of pages in each block */
     uint32  totalBlocks;        /**< The total number of blocks in a device */
-    
+
     uint32  addressBytes;       /**< Number of bytes in the address */
     bool    lsbFirst;           /**< Set to true if the LSB is output first, otherwise msb is first */
     uint32  blockOffset;        /**< Address bits which specify the block number */
     uint32  pageOffset;         /**< Address bits which specify the page number */
     uint32  columnOffset;       /**< Address bits which specify the column number */
-    
-    uint32  eccBytesIdx[ibl_N_ECC_BYTES]; 
+
+    uint8   eccBytesIdx[ibl_N_ECC_BYTES];
                                 /**< Index of each ECC byte in each page data */
-    uint32  badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE]; 
+    uint8   badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
                                 /**< Index of bad block marker in each page data */
 
     uint8   resetCommand;       /**< The command to reset the flash */
     uint8   readCommandPre;     /**< The read command sent before the address */
     uint8   readCommandPost;    /**< The read command sent after the address */
     bool    postCommand;        /**< If TRUE the post command is sent */
-    
+
 } nandDevInfo_t;
-    
-    
+
+
+/**
+ *  @def ibl_N_ENDIANS
+ */
+#define ibl_N_ENDIANS       2  /**< The number of endians supported */
+
+#define ibl_ENDIAN_BIG      0  /**< Big endian */
+#define ibl_ENDIAN_LITTLE   1  /**< Little endian */
+
+/**
+ *  @def ibl_N_IMAGES
+ */
+#define ibl_N_IMAGES        2  /**< The number of boot images supported on the same device */
+
 /**
  *  @brief
  *      This structure is used to control the operation of the NAND boot
@@ -506,28 +518,31 @@ typedef struct nandDevInfo_s
 typedef struct iblNand_s
 {
 
-    int32    bootFormat;        /**< The format of the boot data file. @ref iblBootFormats */                            
-    uint32   bootAddress;       /**< The start address for booting */
-    int32    interface;         /**< The nand interface @ref iblPmemf */
-    iblBinBlob_t blob;          /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
-    
-    
+    int32    bootFormat;                                /**< The format of the boot data file. @ref iblBootFormats */
+    uint32   bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES];  /**< The start address of each image for booting */
+    int32    interface;                                 /**< The nand interface @ref iblPmemf */
+    iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES];     /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+
     nandDevInfo_t nandInfo;     /** Low level device info */
 
 } iblNand_t;
 
 /**
  *  @brief
- *      Nor boot configuration. 
+ *      Nor boot configuration.
  */
 typedef struct iblNor_s
 {
-    int32   bootFormat;         /**<  The format of the boot data file. @ref iblBootFormats */
-    uint32  bootAddress;        /**<  The start address for booting */
-    int32   interface;          /**<  The nor interface. @ref iblPmemIf */
-    iblBinBlob_t blob;          /**<  Used only if the format is ibl_BOOT_FORMAT_BBLOB */
-    
-} iblNor_t;    
+    int32   bootFormat;                                 /**<  The format of the boot data file. @ref iblBootFormats */
+    uint32  bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES];   /**<  The start address for booting */
+    int32   interface;                                  /**<  The nor interface. @ref iblPmemIf */
+    iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES];     /**<  Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+} iblNor_t;
+
+extern uint32 iblEndianIdx;
+extern uint32 iblImageIdx;
 
 /**
  * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
@@ -536,7 +551,7 @@ typedef struct iblNor_s
  * @ingroup iblPmemIf
  * @{
  */
+
 /** @def ibl_PMEM_IF_GPIO - GPIO interface */
 #define  ibl_PMEM_IF_GPIO         0
 
@@ -554,10 +569,10 @@ typedef struct iblNor_s
 
 /** @def ibl_PMEM_IF_SPI */
 #define  ibl_PMEM_IF_SPI          100 /* Interface through SPI */
-    
-/* @} */    
-    
-    
+
+/* @} */
+
+
 /**
  *  @brief
  *      EMIF (nand/nor) configuration
@@ -567,7 +582,7 @@ typedef struct iblEmif_s {
     int16  csSpace;           /**< Chip select space, @ref iblPmemIf */
     int16  busWidth;          /**< Bus width, bits */
     bool   waitEnable;        /**< Valid only for NOR devices */
-    
+
 } iblEmif_t;
 
 /**
@@ -589,11 +604,11 @@ typedef struct iblSpi_s
     int16  csel;            /**<  Chip select value (5 pin). Only 0b10 and 0b01 are valid */
     uint16 c2tdelay;        /**<  Setup time between chip select and the transaction */
     uint16 busFreqMHz;      /**<  Bus speed */
-    
+
 } iblSpi_t;
-    
-    
-    
+
+
+
 /**
  *  @brief
  *      This structure is used to control the programming of the device PLL
@@ -604,22 +619,22 @@ typedef struct iblSpi_s
 typedef struct iblPll_s  {
 
     bool    doEnable;       /**< If true the PLL is configured */
-    
+
     Uint32  prediv;         /**< The pll pre-divisor */
     Uint32  mult;           /**< The pll multiplier */
     Uint32  postdiv;        /**< The pll post divider */
-    
-    Uint32  pllOutFreqMhz;  /**<  The resulting output frequency, required for timer setup */ 
-    
+
+    Uint32  pllOutFreqMhz;  /**<  The resulting output frequency, required for timer setup */
+
 } iblPll_t;
 
 
-/** 
+/**
  *  @defgroup iblPllNum
- * 
+ *
  *  @ingroup iblPllNum
  *  @{
- * 
+ *
  *  @def ibl_MAIN_PLL
  */
 #define ibl_MAIN_PLL    0  /**< The main cpu pll */
@@ -640,7 +655,7 @@ typedef struct iblPll_s  {
 #define ibl_N_PLL_CFGS  (ibl_NET_PLL + 1)
 
 /* @} */
-    
+
 
 /**
  *  @def iblBoot_t
@@ -649,7 +664,7 @@ typedef struct iblPll_s  {
  *  @details
  *      The ibl allows for the configuration for multiple boot attempts. This structure is
  *      used to configure the ibl boot attempt.
- */    
+ */
 typedef struct iblBoot_s
 {
 
@@ -657,62 +672,74 @@ typedef struct iblBoot_s
 
     uint32  priority;           /**< The boot priority. @ref iblPeriphPriority */
     int32   port;               /**< The port to use, or @ref ibl_PORT_FROM_RBL */
-    
+
     union  {
-    
+
         iblEth_t   ethBoot;      /**< Ethernet boot configuration. @ref iblEth_t */
-    
+
         iblNand_t  nandBoot;     /**< NAND boot configuration @ref iblNand_t */
-    
+
         iblNor_t   norBoot;      /**< NOR boot configuration  @ref iblNor_t */
-        
+
     } u;
-    
+
 } iblBoot_t;
-    
+
 
 /**
  * @def ibl_MAGIC_VALUE
  */
-#define ibl_MAGIC_VALUE  0xCEC11EBB  /**< Indicates that the configuration table is valid */
-    
+#define ibl_MAGIC_VALUE  0xCEC11EBC  /**< Indicates that the configuration table is valid */
+
+/**
+ * @def ibl_EVM_TYPE
+ */
+#define ibl_EVM_C6455L  0x10   /**< C6455 Low Cost EVM */
+#define ibl_EVM_C6457L  0x20   /**< C6457 Low Cost EVM */
+#define ibl_EVM_C6472L  0x30   /**< C6472 Low Cost EVM */
+#define ibl_EVM_C6474L  0x40   /**< C6474 Low Cost EVM */
+#define ibl_EVM_C6474M  0x41   /**< C6474 Mez EVM */
+#define ibl_EVM_C6670L  0x50   /**< C6670 Low Cost EVM */
+#define ibl_EVM_C6678L  0x60   /**< C6678 Low Cost EVM */
+
+
 /**
  *  @brief
  *    The main configuration/control structure for the ibl
  *
  *  @details
- *    The operation of the ibl is configured/controlled based on the values in this structure. 
+ *    The operation of the ibl is configured/controlled based on the values in this structure.
  *    This structure resides at a fixed location in the memory map. It can be changed during
  *    the boot operation itself by loading new values into it, but these changes must occur
  *    as part of the boot process itself (not through an asynchronous write through a master
  *    peripheral).
  *
- *    Each boot mode is assigned a priority, with lower values indicating a higher 
+ *    Each boot mode is assigned a priority, with lower values indicating a higher
  *    priority. The lowest valid priority is @ref ibl_LOWEST_BOOT_PRIORITY, and the value
- *    @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral. 
+ *    @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral.
  */
 typedef struct ibl_s
 {
     uint32     iblMagic;                      /**< @ref ibl_MAGIC_VALUE */
-    
+
     iblPll_t   pllConfig[ibl_N_PLL_CFGS];     /**< PLL Configuration. @ref iblPll_t */
-    
+
     iblDdr_t   ddrConfig;                     /**< DDR configuration @ref iblDdr_t  */
-    
+
     iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS];  /**< SGMII boot configuration. @ref iblSgmii_t */
-    
+
     iblMdio_t  mdioConfig;                    /**< MDIO configuration. @ref iblMdio_t */
-    
+
     iblSpi_t   spiConfig;                     /**< SPI configuration @ref iblSpi_s */
-    
+
     iblEmif_t  emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
-    
+
     iblBoot_t  bootModes[ibl_N_BOOT_MODES];   /**< Boot configuration */
-    
+
+    uint16     iblEvmType;                    /**< @ref ibl_EVM_TYPE */
+
     uint16     chkSum;                        /**< Ones complement checksum over the whole config structure */
-    
-    
-     
+
 } ibl_t;
 
 
@@ -754,7 +781,7 @@ extern ibl_t ibl;
  *      @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
  */
 #define ibl_FAIL_CODE_INVALID_I2C_ADDRESS  700      /**< Invalid i2c eeprom address encountered */
+
 /**
  *  @def ibl_FAIL_CODE_BTBL_FAIL
  */
@@ -764,8 +791,8 @@ extern ibl_t ibl;
  *  @def ibl_FAIL_CODE_PA
  */
 #define ibl_FAIL_CODE_PA                    702     /**< Packet Accelerator setup failed */
-   
-   
+
+
 /**
  *  @def ibl_FAIL_CODE_SPI_PARAMS
  */
@@ -815,57 +842,57 @@ extern ibl_t ibl;
 typedef struct iblStatus_s
 {
     uint32 iblMagic;        /**<  The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
-    
+
     uint32 iblVersion;      /**<  The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
-    
+
     uint32 iblFail;         /**<  If non-zero the IBL has encountered a fatal error */
-    
+
     uint32 i2cRetries;      /**<  Count of I2C read retries */
     uint32 i2cDataRetries;  /**<  Number of retries while reading block data from the i2c */
-    
+
     uint32 spiRetries;      /**<  Count of SPI read retries */
     uint32 spiDataRetries;  /**<  Number of retries while reading block data from the spi */
-    
-    uint32 magicRetries;    /**<  Count of I2C/SPI re-reads because the magic number was incorrect */ 
+
+    uint32 magicRetries;    /**<  Count of I2C/SPI re-reads because the magic number was incorrect */
     uint32 mapSizeFail;     /**<  Number of times an invalid map table size was read from the i2c/spi */
     uint32 mapRetries;      /**<  Number of times the checksum failed on the read of the i2c/spi map */
-    
+
     int32  heartBeat;       /**<  An increasing value as long as the boot code is running */
-    
+
     int32  activeBoot;        /**<  Describes the active boot mode @ref iblBootModes */
     int32  activeDevice;      /**<  Describes the active boot peripheral device @ref iblActiveDevice */
     int32  activeFileFormat;  /**<  Describes the format being decoded */
-    
+
     uint32  autoDetectFailCnt;      /**<  Counts the number of times an auto detect of the data format failed */
     uint32  nameDetectFailCnt;      /**<  Counts the number of times an name detect of the data format failed */
-    
+
     uint32 invalidDataFormatSpec;   /**<  Counts the number of times the main boot found an invalid boot format request */
-    
+
     uint32 exitAddress;             /**<  If non-zero the IBL exited and branched to this address */
-    
+
     iblEthBootInfo_t ethParams;     /**<  Last ethernet boot attemp parameters */
-    
-} iblStatus_t;                               
-                               
-extern iblStatus_t iblStatus;                               
 
+} iblStatus_t;
+
+extern iblStatus_t iblStatus;
 
-/** 
+
+/**
  *  @brief
  *      The ibl boot map structure
  *
- *  @details 
+ *  @details
  *      The ibl boot device contains a structure which identifies the location of the big and little
  *      endian ibl images on the external device.
  */
-typedef struct iblBootMap_s 
+typedef struct iblBootMap_s
 {
     uint16  length;         /**<  Size of the structure in bytes */
     uint16  chkSum;         /**<  Value which makes the ones complement checksum over the block equal to 0 or -0 */
-    
+
     uint32  addrLe;         /**<  Base address of the boot tables for the little endian image */
     uint32  configLe;       /**<  Base address of the ibl structure for use with the little endian image */
-    
+
     uint32  addrBe;         /**<  Base address of the boot tables for the big endian image */
     uint32  configBe;       /**<  Base address of the ibl structure for use with the big endian image */
 
@@ -877,5 +904,4 @@ typedef struct iblBootMap_s
 
 
 
-
 #endif /* IBL_H */
index 2bf2103a4dd9e366a1ee09246445f98d00734e66..d9c00d332fdc5e0a75d01228a3f704fb373913c6 100644 (file)
@@ -159,9 +159,14 @@ BOOL DLIF_allocate(struct DLOAD_MEMORY_REQUEST *targ_req)
    /*   load placement or both load and run placement, then we can do the    */
    /*   copy.                                                                */
    /*------------------------------------------------------------------------*/
-   memset(targ_req->host_address, 0, obj_desc->memsz_in_bytes);
-   fseek(f,targ_req->offset,SEEK_SET);
-   fread(targ_req->host_address,obj_desc->objsz_in_bytes,1,f);
+   if (obj_desc->objsz_in_bytes)
+   {
+       /* Do not clear uninitialized data section, so that the section can 
+          be mapped to the same region IBL uses */ 
+       memset(targ_req->host_address, 0, obj_desc->memsz_in_bytes);
+       fseek(f,targ_req->offset,SEEK_SET);
+       fread(targ_req->host_address,obj_desc->objsz_in_bytes,1,f);
+   }
 
    /*------------------------------------------------------------------------*/
    /* Once we have target address for this allocation, add debug information */
index 164f1c45b45fbfc76cd07341ee7aeb7f8b64feb5..5b1e1eea372f71e6450d42bac414f66e72b6404c 100644 (file)
@@ -53,7 +53,6 @@
 #pragma DATA_SECTION(ibl, ".ibl_config_table")
 ibl_t ibl;
 
-
 /**
  * @brief The ibl status table is declared.
  *  
index 23ab6f0b2b6f6d77858973b9af463ab155f2aa2e..065ba993d1e2a59e81eb797f81d8d350f85b0713 100644 (file)
@@ -189,7 +189,7 @@ uint16 swap16val (uint16 v)
  */
 void iblSwap (void)
 {
-    int i;
+    int i, j, k;
 
     ibl.iblMagic = swap32val (ibl.iblMagic);
 
@@ -288,11 +288,23 @@ void iblSwap (void)
 
         }  else if (ibl.bootModes[i].bootMode == ibl_BOOT_MODE_NAND)  {
             ibl.bootModes[i].u.nandBoot.bootFormat             = swap32val(ibl.bootModes[i].u.nandBoot.bootFormat);
-            ibl.bootModes[i].u.nandBoot.bootAddress            = swap32val(ibl.bootModes[i].u.nandBoot.bootAddress);
+            for (j = 0; j < ibl_N_ENDIANS; j++)
+            {
+                for (k = 0; k < ibl_N_IMAGES; k++)
+                {
+                    ibl.bootModes[i].u.nandBoot.bootAddress[j][k] = swap32val(ibl.bootModes[i].u.nandBoot.bootAddress[j][k]);
+                }
+            }
             ibl.bootModes[i].u.nandBoot.interface              = swap32val(ibl.bootModes[i].u.nandBoot.interface);
-            ibl.bootModes[i].u.nandBoot.blob.startAddress      = swap32val(ibl.bootModes[i].u.nandBoot.blob.startAddress);
-            ibl.bootModes[i].u.nandBoot.blob.sizeBytes         = swap32val(ibl.bootModes[i].u.nandBoot.blob.sizeBytes);
-            ibl.bootModes[i].u.nandBoot.blob.branchAddress     = swap32val(ibl.bootModes[i].u.nandBoot.blob.branchAddress);
+            for (j = 0; j < ibl_N_ENDIANS; j++)
+            {
+                for (k = 0; k < ibl_N_IMAGES; k++)
+                {
+                    ibl.bootModes[i].u.nandBoot.blob[j][k].startAddress  = swap32val(ibl.bootModes[i].u.nandBoot.blob[j][k].startAddress);
+                    ibl.bootModes[i].u.nandBoot.blob[j][k].sizeBytes     = swap32val(ibl.bootModes[i].u.nandBoot.blob[j][k].sizeBytes);
+                    ibl.bootModes[i].u.nandBoot.blob[j][k].branchAddress = swap32val(ibl.bootModes[i].u.nandBoot.blob[j][k].branchAddress);
+                }
+            }
             ibl.bootModes[i].u.nandBoot.nandInfo.busWidthBits  = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.busWidthBits);
             ibl.bootModes[i].u.nandBoot.nandInfo.pageSizeBytes = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.pageSizeBytes);
             ibl.bootModes[i].u.nandBoot.nandInfo.pageEccBytes  = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.pageEccBytes);
@@ -303,15 +315,26 @@ void iblSwap (void)
             ibl.bootModes[i].u.nandBoot.nandInfo.blockOffset   = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.blockOffset);
             ibl.bootModes[i].u.nandBoot.nandInfo.pageOffset    = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.pageOffset);
             ibl.bootModes[i].u.nandBoot.nandInfo.columnOffset  = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.columnOffset);
-            ibl.bootModes[i].u.nandBoot.nandInfo.postCommand   = swap32val(ibl.bootModes[i].u.nandBoot.nandInfo.postCommand);
-
+            ibl.bootModes[i].u.nandBoot.nandInfo.postCommand   = swap16val(ibl.bootModes[i].u.nandBoot.nandInfo.postCommand);
         }  else if (ibl.bootModes[i].bootMode == ibl_BOOT_MODE_NOR)  {
             ibl.bootModes[i].u.norBoot.bootFormat         = swap32val(ibl.bootModes[i].u.norBoot.bootFormat);
-            ibl.bootModes[i].u.norBoot.bootAddress        = swap32val(ibl.bootModes[i].u.norBoot.bootAddress);
+            for (j = 0; j < ibl_N_ENDIANS; j++)
+            {
+                for (k = 0; k < ibl_N_IMAGES; k++)
+                {
+                    ibl.bootModes[i].u.norBoot.bootAddress[j][k] = swap32val(ibl.bootModes[i].u.norBoot.bootAddress[j][k]);
+                }
+            }
             ibl.bootModes[i].u.norBoot.interface          = swap32val(ibl.bootModes[i].u.norBoot.interface);
-            ibl.bootModes[i].u.norBoot.blob.startAddress  = swap32val(ibl.bootModes[i].u.norBoot.blob.startAddress);
-            ibl.bootModes[i].u.norBoot.blob.sizeBytes     = swap32val(ibl.bootModes[i].u.norBoot.blob.sizeBytes);
-            ibl.bootModes[i].u.norBoot.blob.branchAddress = swap32val(ibl.bootModes[i].u.norBoot.blob.branchAddress);
+            for (j = 0; j < ibl_N_ENDIANS; j++)
+            {
+                for (k = 0; k < ibl_N_IMAGES; k++)
+                {
+                    ibl.bootModes[i].u.norBoot.blob[j][k].startAddress  = swap32val(ibl.bootModes[i].u.norBoot.blob[j][k].startAddress);
+                    ibl.bootModes[i].u.norBoot.blob[j][k].sizeBytes     = swap32val(ibl.bootModes[i].u.norBoot.blob[j][k].sizeBytes);
+                    ibl.bootModes[i].u.norBoot.blob[j][k].branchAddress = swap32val(ibl.bootModes[i].u.norBoot.blob[j][k].branchAddress);
+                }
+            }
 
         }
 
index 3bcac31e9f124cebcf0983467529e146f858db7b..6cd57996e3965de4f10db7fcb089de19b123c0e5 100644 (file)
 #include "ibl_elf.h"
 #include <string.h>
 
+extern cregister unsigned int IER;
+
+uint32 iblEndianIdx = 0;
+uint32 iblImageIdx = 0;
+
 /**
  *  @brief
  *      Data structures shared between the 1st and 2nd stage IBL load
@@ -231,6 +236,7 @@ void iblPmemCfg (int32 interface, int32 port, bool enableNand)
 void main (void)
 {
     int32 i, j;
+    UINT32 v, boot_mode_idx, boot_para_idx;
 
     /* Initialize the status structure */
     iblMemset (&iblStatus, 0, sizeof(iblStatus_t));
@@ -262,49 +268,124 @@ void main (void)
     /* Try booting forever */
     for (;;)  {
 
-        /* Start looping through the boot modes to find the one with the highest priority
-         * value, and try to boot it. */
-        for (i = ibl_HIGHEST_PRIORITY; i < ibl_LOWEST_PRIORITY; i++)  {
-
-            for (j = 0; j < ibl_N_BOOT_MODES; j++)  {
-
-                if (ibl.bootModes[j].priority == i)  {
-
-                    iblStatus.activeBoot = ibl.bootModes[j].bootMode;
-
-                    switch (ibl.bootModes[j].bootMode)  {
-
-
-                        #ifndef EXCLUDE_ETH
-                            case ibl_BOOT_MODE_TFTP:
-                                    iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
-                                    iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[j].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
-                                    iblEthBoot (j);
-                                    break;
-                        #endif
-
-                        #if ((!defined(EXCLUDE_NAND_EMIF)) )                                    
-                            case ibl_BOOT_MODE_NAND:
-                                    iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
-                                    iblNandBoot (j);
-                                    break;
-                        #endif
+#ifndef EXCLUDE_MULTI_BOOT
+        v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+        if (
+            (v == DEVICE_C6618_JTAG_ID_VAL)         || 
+            (v == DEVICE_C6616_JTAG_ID_VAL)
+           )
+        {
+            IER = 0;
+
+            /* For C66x devices, check the DEVSTAT register to find which image on which device to boot. */
+            v = DEVICE_REG32_R(DEVICE_REG_DEVSTAT);
+            
+            /* Get the Endianness */
+            if (ibl_N_ENDIANS == 1)
+            {
+                iblEndianIdx = 0;
+            }
+            else
+            {
+                if (v & ibl_ENDIAN_LITTLE)
+                {
+                    iblEndianIdx = 0;
+                }
+                else
+                {
+                    iblEndianIdx = 1;
+                }
+            }
 
-                        #if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
-                            case ibl_BOOT_MODE_NOR:
-                                    iblPmemCfg (ibl.bootModes[j].u.norBoot.interface, ibl.bootModes[j].port, TRUE);
-                                    iblNorBoot (j);
-                                    break;
-                        #endif
+            /* Get the boot mode index */
+            boot_para_idx = BOOT_READ_BITFIELD(v,8,4);
 
+            /* Only 1 image supported for TFTP boot */
+            if (boot_para_idx > (ibl_N_IMAGES*(ibl_N_BOOT_MODES-1)))
+            {
+                /* boot parameter index not supported */
+                continue;
+            }
+            boot_mode_idx = boot_para_idx/ibl_N_IMAGES;
+            /* Get the boot image index */
+            iblImageIdx == boot_para_idx & (ibl_N_IMAGES - 1);
+
+            iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
+
+            switch (ibl.bootModes[boot_mode_idx].bootMode)  
+            {
+#ifndef EXCLUDE_ETH
+            case ibl_BOOT_MODE_TFTP:
+                iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+                iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[boot_mode_idx].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+                iblEthBoot (boot_mode_idx);
+                break;
+#endif
+                
+#if ((!defined(EXCLUDE_NAND_EMIF)) )                                    
+            case ibl_BOOT_MODE_NAND:
+                iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+                memset ((void *)0x80000000, 0, 0x20000000);
+                iblNandBoot (boot_mode_idx);
+                break;
+#endif
+                
+#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
+            case ibl_BOOT_MODE_NOR:
+                iblPmemCfg (ibl.bootModes[boot_mode_idx].u.norBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+                iblNorBoot (boot_mode_idx);
+                break;
+#endif
+            }
+            iblStatus.heartBeat += 1;
+        }
+        else
+#endif
+        {
+            
+           /* For C64x devices, loop through the boot modes to find the one with the highest priority
+            * value, and try to boot it. */
+            for (i = ibl_HIGHEST_PRIORITY; i < ibl_LOWEST_PRIORITY; i++)  {
+                
+                for (j = 0; j < ibl_N_BOOT_MODES; j++)  {
+                    
+                    if (ibl.bootModes[j].priority == i)  {
+                        
+                        iblStatus.activeBoot = ibl.bootModes[j].bootMode;
+                        
+                        switch (ibl.bootModes[j].bootMode)  {
+                            
+                            
+#ifndef EXCLUDE_ETH
+                        case ibl_BOOT_MODE_TFTP:
+                            iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+                            iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[j].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+                            iblEthBoot (j);
+                            break;
+#endif
+                            
+#if ((!defined(EXCLUDE_NAND_EMIF)) )                                    
+                        case ibl_BOOT_MODE_NAND:
+                            iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
+                            iblNandBoot (j);
+                            break;
+#endif
+                            
+#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
+                        case ibl_BOOT_MODE_NOR:
+                            iblPmemCfg (ibl.bootModes[j].u.norBoot.interface, ibl.bootModes[j].port, TRUE);
+                            iblNorBoot (j);
+                            break;
+#endif
+                            
+                        }
                     }
+                    
+                    iblStatus.heartBeat += 1;
+                    
                 }
-
-            iblStatus.heartBeat += 1;
-
             }
         }
-
     }
 
 
index 6885e3634630a7f4d9e15801cf5b1196acff5aa0..2ac143182cf2162139321bba244522f40bb0bf54 100644 (file)
@@ -57,6 +57,7 @@
 #*                     [SPI=no]                                                        /* Disables SPI */
 #*                     [I2C=no]                                                        /* Disables I2C */
 #*                     [EMIF=no]                                                       /* Disables EMIF */
+#*                     [MULTI_BOOT=no]                                         /* Disables Multi-boot feature */
 #*                     [SPI_MODE=<0,1,2,3>]                            /* Selects the SPI operating mode */
 #*                     [SPI_ADDR_WIDTH=<16,24>]                        /* Selects the SPI address width */
 #*                     [SPI_NPIN=<4,5>]                                        /* Selects the number of pins on the interface */
@@ -178,6 +179,10 @@ ifeq ($(EMIF),no)
 
 endif
 
+ifeq ($(MULTI_BOOT),no)
+  CEXCLUDES+= MULTI_BOOT
+endif
+
 # The endian of the build. The default target builds a single ROM image with both endians present
 ifeq ($(ENDIAN),big)
  ENDIAN_MODE=big
@@ -265,30 +270,30 @@ $(IBLS_C6X):
 # Configurations for individual evms
 # The c6455 EVM has a 128k eeprom (64k at 0x50, 64k at 0x51), so both endians are built with full functionality
 evm_c6455:
-       make -f makestg1 ARCH=c64x TARGET=c6455 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES= c6455
+       make -f makestg1 ARCH=c64x TARGET=c6455 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES='MULTI_BOOT' c6455
 
 # The c6472 EVM has a 128k eeprom (64k at 0x50, 64k at 0x51), so both endians are built with full functionality
 evm_c6472:
-       make -f makestg1 ARCH=c64x TARGET=c6472 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES= c6472
+       make -f makestg1 ARCH=c64x TARGET=c6472 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES='MULTI_BOOT' c6472
 
 # The 6474 EVM has a 32k eeprom. A stripped down version is build with only one endian.
 evm_c6474:
-       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS' I2C_SIZE_BYTES=0x8000 c6474
+       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' I2C_SIZE_BYTES=0x8000 c6474
        cp ibl_c6474/i2crom.dat ibl_c6474/i2crom_0x50_c6474_le.dat
-       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS' I2C_SIZE_BYTES=0x8000 c6474
+       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' I2C_SIZE_BYTES=0x8000 c6474
        cp ibl_c6474/i2crom.dat ibl_c6474/i2crom_0x50_c6474_be.dat
 
 evm_c6474l:
-       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS' c6474
+       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' c6474
        cp ibl_c6474/i2crom.dat ibl_c6474/i2crom_0x50_c6474l_le.dat
-       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS' c6474
+       make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' c6474
        cp ibl_c6474/i2crom.dat ibl_c6474/i2crom_0x50_c6474l_be.dat
 
 # The 6457 EVM
 evm_c6457:
-       make -f makestg1 ARCH=c64x TARGET=c6457 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS' c6457
+       make -f makestg1 ARCH=c64x TARGET=c6457 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=little CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' c6457
        cp ibl_c6457/i2crom.dat ibl_c6457/i2crom_0x50_c6457_le.dat
-       make -f makestg1 ARCH=c64x TARGET=c6457 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS' c6457
+       make -f makestg1 ARCH=c64x TARGET=c6457 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS MULTI_BOOT' c6457
        cp ibl_c6457/i2crom.dat ibl_c6457/i2crom_0x50_c6457_be.dat
 
 # The 6608 EVM
@@ -297,17 +302,14 @@ EVM_6608_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL
 evm_c6608:
        make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
 
-# The 6678 EVM SPI/NOR Boot
-EVM_6678_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
-
-evm_c6678_spi:
-       make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+# The 667x EVM SPI/NOR Boot
+EVM_667x_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
 
-evm_c6678_i2c:
-       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+evm_c667x_spi:
+       make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
 
-evm_c6670_i2c:
-       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+evm_c667x_i2c:
+       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
 
 test_c661x:
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c661x
@@ -387,6 +389,8 @@ clean:
        find ../ -name *.dc | xargs rm -f
        find ../ -name *.oa | xargs rm -f
        find ../ -name *.da | xargs rm -f
+       find ../ -name *.tmp | xargs rm -f
+       find ../ -name cdefdep | xargs rm -f
 
 
 
index 456c77d80250cd7eac0ce85be9a28b92006f2fbc..95e4e33f115a499fc12a525dc2d78469d72d5a99 100644 (file)
@@ -24,9 +24,9 @@ MEMORY
        CFG       :  origin = 0x81b800, length = 0x0300
        STAT      :  origin = 0x81bb00, length = 0x0200
 
-       LINKRAM   :  origin = 0x1081bd00, length = 0x0200
-       CPPIRAM   :  origin = 0x1081bf00, length = 0x0200
-       PKTRAM    :  origin = 0x1081c100, length = 0x0800
+       LINKRAM   :  origin = 0x1081be00, length = 0x0200
+       CPPIRAM   :  origin = 0x1081c000, length = 0x0200
+       PKTRAM    :  origin = 0x1081c200, length = 0x0800
 }
 
 
index 0f85c1660abe862f20ab40605cb5fbc07bd8b091..23062d5502c8cd6cbcf397379a719342f3a3a4d7 100644 (file)
@@ -127,9 +127,6 @@ else
  endif
 endif
 
-ifeq ($(HAS_SPI),0)
-    SPI_CFG=    
-endif
 
 i2crom:
        $(CC) -ppo -I../cfg/$(TARGET) $(I2C_DEFS) ibl_$(TARGET)/$@.map.pre
index 7ba461c7a7d18e6646221ed66283e974b25ded87..5dd5ff1d438e370f628514e18b70d4f87caa40ae 100644 (file)
@@ -1,38 +1,39 @@
-@REM ******************************************************************************\r
-@REM * FILE PURPOSE: Environment Setup for building Bootloader\r
-@REM ******************************************************************************\r
-@REM * FILE NAME: setupenv.bat\r
-@REM *\r
-@REM * DESCRIPTION: \r
-@REM *  Configures and sets up the Build Environment for Bootloader in DOS environment. \r
-@REM *  \r
-@REM *  Customers are expected to modify this file as per their build environment.\r
-@REM *\r
-@REM * USAGE:\r
-@REM *  setupenv.bat  \r
-@REM *\r
-@REM * Copyright (C) 2010, Texas Instruments, Inc.\r
-@REM *****************************************************************************\r
-\r
-@echo off\r
-\r
-REM  Setup the ibl build environment if using cygwin for build\r
-\r
-REM Modify following lines based on target environment for the toolset installed \r
-REM Dependency is related to path for Cygwin and CGEN installed\r
-\r
-REM Specify the path to cygwin binaries and the code gen tools\r
-REM If the path has directory names with spaces use the below format to specify\r
-REM for e.g PATH=G:\cygwin\bin;C:\PROGRA~1\TEXASI~1\C6000C~1.12\bin\r
-set PATH=G:\cygwin\bin;t:\c6xx\cgen6_1_12\c6000\cgtools\bin\r
-\r
-REM Specify the base directory of the c6000 compiler with UNIX style path separator\r
-set TOOLSC6X=t:/c6xx/cgen6_1_12/c6000/cgtools\r
-\r
-REM Specify the base directory of the c6000 compiler with DOS style path separator\r
-set TOOLSC6XDOS=t:\c6xx\cgen6_1_12\c6000\cgtools\r
-\r
-REM # Don't modify the below variables. They are derived from the above definitions \r
-set PATH=%PATH%;%SystemRoot%\system32;%SystemRoot%;\r
-set BISONSKEL=yacc.c\r
-\r
+@REM ******************************************************************************
+@REM * FILE PURPOSE: Environment Setup for building Bootloader
+@REM ******************************************************************************
+@REM * FILE NAME: setupenv.bat
+@REM *
+@REM * DESCRIPTION: 
+@REM *  Configures and sets up the Build Environment for Bootloader in DOS environment. 
+@REM *  
+@REM *  Customers are expected to modify this file as per their build environment.
+@REM *
+@REM * USAGE:
+@REM *  setupenv.bat  
+@REM *
+@REM * Copyright (C) 2010, Texas Instruments, Inc.
+@REM *****************************************************************************
+
+@echo off
+
+REM  Setup the ibl build environment if using cygwin for build
+
+REM Modify following lines based on target environment for the toolset installed 
+REM Dependency is related to path for Cygwin and CGEN installed
+
+REM Specify the path to cygwin binaries and the code gen tools
+REM If the path has directory names with spaces use the below format to specify
+REM for e.g PATH=G:\cygwin\bin;C:\PROGRA~1\TEXASI~1\C6000C~1.12\bin
+set PATH=G:\cygwin\bin;t:\c6xx\cgen6_1_12\c6000\cgtools\bin
+
+REM Specify the base directory of the c6000 compiler with UNIX style path separator
+set TOOLSC6X=t:/c6xx/cgen6_1_12/c6000/cgtools
+
+REM Specify the base directory of the c6000 compiler with DOS style path separator
+set TOOLSC6XDOS=t:\c6xx\cgen6_1_12\c6000\cgtools
+
+REM # Don't modify the below variables. They are derived from the above definitions 
+set PATH=%PATH%;%SystemRoot%\system32;%SystemRoot%;
+set BISONSKEL=yacc.c
+
+
index c4f3e7e479bd7841c74811e07aea32bc35bd26ab..b155f66d014c74a6a8dd02e058cca798055fe7e5 100644 (file)
@@ -81,7 +81,7 @@ void iblNandBoot (int32 eIdx)
         return;
 
 
-    entry = iblBoot (&nand_boot_module, ibl.bootModes[eIdx].u.nandBoot.bootFormat, &ibl.bootModes[eIdx].u.nandBoot.blob);
+    entry = iblBoot (&nand_boot_module, ibl.bootModes[eIdx].u.nandBoot.bootFormat, &ibl.bootModes[eIdx].u.nandBoot.blob[iblEndianIdx][iblImageIdx]);
 
     (*nand_boot_module.close)();
 
index ece599e0d24eb99b6d5b4d7cde63021b5fc564e1..43ef2fe0f8398880439d1ca6f11da0463619d793 100644 (file)
@@ -62,7 +62,7 @@ void iblNorBoot (int32 eIdx)
         return;
 
 
-    entry = iblBoot (&nor_boot_module, ibl.bootModes[eIdx].u.norBoot.bootFormat, &ibl.bootModes[eIdx].u.norBoot.blob);
+    entry = iblBoot (&nor_boot_module, ibl.bootModes[eIdx].u.norBoot.bootFormat, &ibl.bootModes[eIdx].u.norBoot.blob[iblEndianIdx][iblImageIdx]);
 
     (*nor_boot_module.close)();
 
index fba6a7d8ecfa243fab5d688f1e1ff66280640e4b..a7ce68b0c12e0c046340e3a490c2580c756358f0 100755 (executable)
@@ -1,7 +1,7 @@
 #define TRUE  1
 #define FALSE 0
 
-#define ibl_MAGIC_VALUE                 0xCEC11EBB
+#define ibl_MAGIC_VALUE                 0xCEC11EBC
 
 #define ibl_HIGHEST_PRIORITY     1  
 #define ibl_LOWEST_PRIORITY     10
 #define  ibl_EMIF4_ENABLE_eccRange2                   (1 << 21)
 #define  ibl_EMIF4_ENABLE_rdWrtExcThresh              (1 << 22)
 #define  ibl_BOOT_EMIF4_ENABLE_ALL                    0x007fffff
+
+
+#define ibl_EVM_C6455L  0x10   /**< C6455 Low Cost EVM */
+#define ibl_EVM_C6457L  0x20   /**< C6457 Low Cost EVM */
+#define ibl_EVM_C6472L  0x30   /**< C6472 Low Cost EVM */
+#define ibl_EVM_C6474L  0x40   /**< C6474 Low Cost EVM */
+#define ibl_EVM_C6474M  0x41   /**< C6474 Mez EVM */
+#define ibl_EVM_C6670L  0x50   /**< C6670 Low Cost EVM */
+#define ibl_EVM_C6678L  0x60   /**< C6678 Low Cost EVM */
     
 /* @} */  
 
@@ -75,6 +84,7 @@ menuitem "EVM c6472 IBL";
 hotmenu setConfig_c6472()
 {
     ibl.iblMagic = ibl_MAGIC_VALUE;
+    ibl.iblEvmType = ibl_EVM_C6472L;
 
     ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
     ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
@@ -98,8 +108,8 @@ hotmenu setConfig_c6472()
     ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
 
     /* SGMII not present */
-       ibl.sgmiiConfig[0].configure = FALSE;
-       ibl.sgmiiConfig[1].configure = FALSE;
+    ibl.sgmiiConfig[0].configure = FALSE;
+    ibl.sgmiiConfig[1].configure = FALSE;
 
     /* MDIO configuration */
     ibl.mdioConfig.nMdioOps = 8;
@@ -119,14 +129,14 @@ hotmenu setConfig_c6472()
     /* spiConfig and emifConfig not needed */
 
     /* Ethernet configuration for Boot mode 0 */
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-       ibl.bootModes[0].port     = 0;
+    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[0].port     = 0;
 
     /* Bootp is disabled. The server and file name are provided here */
     ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+    ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+    ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
     ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
     /* Even though the entire range of DDR2 is chosen, the load will
@@ -165,7 +175,7 @@ hotmenu setConfig_c6472()
     ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
 
     /* Alternative bootMode not configured for now */
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
 
     ibl.chkSum = 0;
 }
@@ -176,6 +186,7 @@ menuitem "EVM c6474 Mez IBL";
 hotmenu setConfig_c6474()
 {
     ibl.iblMagic = ibl_MAGIC_VALUE;
+    ibl.iblEvmType = ibl_EVM_C6474M;
 
     ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
     ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
@@ -199,7 +210,7 @@ hotmenu setConfig_c6474()
     ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
 
     /* SGMII 0 is present */
-       ibl.sgmiiConfig[0].configure = TRUE;
+    ibl.sgmiiConfig[0].configure = TRUE;
     ibl.sgmiiConfig[0].adviseAbility = 0x9801;
     ibl.sgmiiConfig[0].control       = 0x20;
     ibl.sgmiiConfig[0].txConfig      = 0x00000ea3;
@@ -207,7 +218,7 @@ hotmenu setConfig_c6474()
     ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
 
     /* There is no port 1 on the 6474 */
-       ibl.sgmiiConfig[1].configure = FALSE;
+    ibl.sgmiiConfig[1].configure = FALSE;
 
     /* MDIO configuration */
     ibl.mdioConfig.nMdioOps = 8;
@@ -227,14 +238,14 @@ hotmenu setConfig_c6474()
     /* spiConfig and emifConfig not needed */
 
     /* Ethernet configuration for Boot mode 0 */
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-       ibl.bootModes[0].port     = 0;
+    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[0].port     = 0;
 
     /* Bootp is disabled. The server and file name are provided here */
     ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+    ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+    ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
     ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
     SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    10,218,109,35);
@@ -273,7 +284,7 @@ hotmenu setConfig_c6474()
     ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
 
     /* Alternative bootMode not configured for now */
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
 
     ibl.chkSum = 0;
 }
@@ -283,6 +294,7 @@ menuitem "EVM c6474 Lite EVM IBL";
 hotmenu setConfig_c6474lite()
 {
     ibl.iblMagic = ibl_MAGIC_VALUE;
+    ibl.iblEvmType = ibl_EVM_C6474L;
 
     ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
     ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
@@ -306,7 +318,7 @@ hotmenu setConfig_c6474lite()
     ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
 
     /* SGMII 0 is present */
-       ibl.sgmiiConfig[0].configure = TRUE;
+    ibl.sgmiiConfig[0].configure = TRUE;
     ibl.sgmiiConfig[0].adviseAbility = 0x9801;
     ibl.sgmiiConfig[0].control       = 0x20;
     ibl.sgmiiConfig[0].txConfig      = 0x00000e23;
@@ -314,7 +326,7 @@ hotmenu setConfig_c6474lite()
     ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
 
     /* There is no port 1 on the 6474 */
-       ibl.sgmiiConfig[1].configure = FALSE;
+    ibl.sgmiiConfig[1].configure = FALSE;
 
     /* MDIO configuration */
     ibl.mdioConfig.nMdioOps = 5;
@@ -331,14 +343,14 @@ hotmenu setConfig_c6474lite()
     /* spiConfig and emifConfig not needed */
 
     /* Ethernet configuration for Boot mode 0 */
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-       ibl.bootModes[0].port     = 0;
+    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[0].port     = 0;
 
     /* Bootp is disabled. The server and file name are provided here */
     ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+    ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+    ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
     ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
     SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    158,218,100,114);
@@ -379,7 +391,7 @@ hotmenu setConfig_c6474lite()
     ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
 
     /* Alternative bootMode not configured for now */
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
 
     ibl.chkSum = 0;
 }
@@ -389,6 +401,7 @@ menuitem "EVM c6457 EVM IBL";
 hotmenu setConfig_c6457()
 {
     ibl.iblMagic = ibl_MAGIC_VALUE;
+    ibl.iblEvmType = ibl_EVM_C6457L;
 
     ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
     ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
@@ -412,7 +425,7 @@ hotmenu setConfig_c6457()
     ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
 
     /* SGMII 0 is present */
-       ibl.sgmiiConfig[0].configure = TRUE;
+    ibl.sgmiiConfig[0].configure = TRUE;
     ibl.sgmiiConfig[0].adviseAbility = 0x9801;
     ibl.sgmiiConfig[0].control       = 0x20;
     ibl.sgmiiConfig[0].txConfig      = 0x00000e21;
@@ -420,7 +433,7 @@ hotmenu setConfig_c6457()
     ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
 
     /* There is no port 1 on the 6457 */
-       ibl.sgmiiConfig[1].configure = FALSE;
+    ibl.sgmiiConfig[1].configure = FALSE;
 
     /* MDIO configuration */
     ibl.mdioConfig.nMdioOps = 5;
@@ -436,14 +449,14 @@ hotmenu setConfig_c6457()
     /* spiConfig and emifConfig not needed */
 
     /* Ethernet configuration for Boot mode 0 */
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-       ibl.bootModes[0].port = 0;
+    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[0].port = 0;
 
     /* Bootp is disabled. The server and file name are provided here */
     ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+    ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+    ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
     ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
     SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    158,218,100,115);
@@ -483,7 +496,7 @@ hotmenu setConfig_c6457()
     ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
 
     /* Alternative bootMode not configured for now */
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
 
     ibl.chkSum = 0;
 }
@@ -493,6 +506,7 @@ menuitem "EVM c6455 IBL";
 hotmenu setConfig_c6455()
 {
     ibl.iblMagic = ibl_MAGIC_VALUE;
+    ibl.iblEvmType = ibl_EVM_C6455L;
 
     ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
     ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
@@ -516,8 +530,8 @@ hotmenu setConfig_c6455()
     ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
 
     /* SGMII not present */
-       ibl.sgmiiConfig[0].configure = FALSE;
-       ibl.sgmiiConfig[1].configure = FALSE;
+    ibl.sgmiiConfig[0].configure = FALSE;
+    ibl.sgmiiConfig[1].configure = FALSE;
 
     /* MDIO configuration */
     ibl.mdioConfig.nMdioOps = 0;
@@ -529,14 +543,14 @@ hotmenu setConfig_c6455()
     /* spiConfig and emifConfig not needed */
 
     /* Ethernet configuration for Boot mode 0 */
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-       ibl.bootModes[0].port     = 0;
+    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[0].port     = 0;
 
     /* Bootp is disabled. The server and file name are provided here */
     ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
-    ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+    ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+    ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
     ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
     SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    158,218,100,118);
@@ -576,7 +590,7 @@ hotmenu setConfig_c6455()
     ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
 
     /* Alternative bootMode not configured for now */
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
 
     ibl.chkSum = 0;
 }
@@ -587,6 +601,7 @@ menuitem "EVM c6678 IBL";
 hotmenu setConfig_c6678_main()
 {
        ibl.iblMagic = ibl_MAGIC_VALUE;
+       ibl.iblEvmType = ibl_EVM_C6678L;
 
        /* Main PLL: 100 MHz reference, 1GHz output */
        ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;
@@ -596,7 +611,7 @@ hotmenu setConfig_c6678_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
@@ -675,105 +690,108 @@ hotmenu setConfig_c6678_main()
        ibl.bootModes[0].port     = 0;
 
        ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
-       ibl.bootModes[0].u.norBoot.bootAddress  = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;
        ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
-    ibl.bootModes[0].u.norBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob.sizeBytes     = 0x80000;          /* 512 KB */
-    ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+    ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[1].port     = 0;
+
+    ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_BBLOB;
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.interface         = ibl_PMEM_IF_CHIPSEL_2;
+
+    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits  = 8;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes  = 16;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+    ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks   = 4096;
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes  = 4;
+    ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst      = TRUE;
+    ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset   = 14;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset    = 9;
+    ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset  = 0;
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0]  = 0; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1]  = 1; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2]  = 2; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3]  = 3; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4]  = 4; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5]  = 6; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6]  = 7; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7]  = 13; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8]  = 14; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9]  = 15; 
+    
+    ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+    ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
 
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
-       ibl.bootModes[1].port     = ibl_PORT_SWITCH_ALL;
+    ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand    = 0xff;
+    ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre  = 0;
+    ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+    ibl.bootModes[1].u.nandBoot.nandInfo.postCommand     = FALSE;
+    
+       ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+       ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+       ibl.bootModes[2].port     = ibl_PORT_SWITCH_ALL;
 
-       ibl.bootModes[1].u.ethBoot.doBootp          = FALSE;
-       ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
-       ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
-       ibl.bootModes[1].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_ELF;
+       ibl.bootModes[2].u.ethBoot.doBootp          = FALSE;
+       ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+       ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+       ibl.bootModes[2].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
 
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr,    192,168,1,100);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp,  192,168,1,101);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask,   255,255,255,0);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr,    192,168,2,100);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp,  192,168,2,101);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask,   255,255,255,0);
 
     /* Use the e-fuse value */
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
-
-
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0]  = 'a';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1]  = 'p';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2]  = 'p';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3]  = '.';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4]  = 'o';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5]  = 'u';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6]  = 't';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
-
-    ibl.bootModes[1].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
-    ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
-
-       ibl.chkSum = 0;
-}
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0]  = 'a';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1]  = 'p';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2]  = 'p';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3]  = '.';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4]  = 'o';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5]  = 'u';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6]  = 't';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
 
-hotmenu setConfig_c6678_emac()
-{
-    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY+1;
-    ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
-}
-
-hotmenu setConfig_c6678_nand()
-{
-    /* Nand boot is higher priority */
-    ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NAND;
-    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
-    ibl.bootModes[0].port     = 0;
-
-    ibl.bootModes[0].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_ELF;
-    ibl.bootModes[0].u.nandBoot.bootAddress      = 0;
-    ibl.bootModes[0].u.nandBoot.interface         = ibl_PMEM_IF_CHIPSEL_2;
-    ibl.bootModes[0].u.nandBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.nandBoot.blob.sizeBytes     = 0x80000;          /* 512 KB */
-    ibl.bootModes[0].u.nandBoot.blob.branchAddress = 0x80000000;       /* Base address of DDR2 */
-
-    ibl.bootModes[0].u.nandBoot.nandInfo.busWidthBits  = 8;
-    ibl.bootModes[0].u.nandBoot.nandInfo.pageSizeBytes = 512;
-    ibl.bootModes[0].u.nandBoot.nandInfo.pageEccBytes  = 16;
-    ibl.bootModes[0].u.nandBoot.nandInfo.pagesPerBlock = 32;
-    ibl.bootModes[0].u.nandBoot.nandInfo.totalBlocks   = 4096;
-
-    ibl.bootModes[0].u.nandBoot.nandInfo.addressBytes  = 4;
-    ibl.bootModes[0].u.nandBoot.nandInfo.lsbFirst      = TRUE;
-    ibl.bootModes[0].u.nandBoot.nandInfo.blockOffset   = 14;
-    ibl.bootModes[0].u.nandBoot.nandInfo.pageOffset    = 9;
-    ibl.bootModes[0].u.nandBoot.nandInfo.columnOffset  = 0;
-
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[0]  = 0; 
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[1]  = 1; 
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[2]  = 2; 
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[3]  = 3; 
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[4]  = 6; 
-    ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[5]  = 7; 
-
-    ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
-    ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xffff;
-
-    ibl.bootModes[0].u.nandBoot.nandInfo.resetCommand    = 0xff;
-    ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPre  = 0;
-    ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPost = 0;
-    ibl.bootModes[0].u.nandBoot.nandInfo.postCommand     = FALSE;
+    ibl.chkSum = 0;
 }
 
 menuitem "EVM c6670 IBL";
@@ -781,6 +799,7 @@ menuitem "EVM c6670 IBL";
 hotmenu setConfig_c6670_main()
 {
        ibl.iblMagic = ibl_MAGIC_VALUE;
+       ibl.iblEvmType = ibl_EVM_C6670L;
 
        /* Main PLL: 122.88 MHz reference, 983 MHz output */
        ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;
@@ -869,61 +888,107 @@ hotmenu setConfig_c6670_main()
        ibl.bootModes[0].port     = 0;
 
        ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
-       ibl.bootModes[0].u.norBoot.bootAddress  = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;
        ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
-    ibl.bootModes[0].u.norBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob.sizeBytes     = 0x80000;          /* 512 KB */
-    ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000;       /* Base address of DDR2 */
-
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
-       ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
-       ibl.bootModes[1].port     = ibl_PORT_SWITCH_ALL;
+    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+
+    ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+    ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+    ibl.bootModes[1].port     = 0;
+
+    ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_BBLOB;
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.interface         = ibl_PMEM_IF_GPIO;
+
+    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits  = 8;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes  = 16;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+    ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks   = 4096;
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes  = 4;
+    ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst      = TRUE;
+    ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset   = 14;
+    ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset    = 9;
+    ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset  = 0;
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0]  = 0; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1]  = 1; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2]  = 2; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3]  = 3; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4]  = 4; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5]  = 6; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6]  = 7; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7]  = 13; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8]  = 14; 
+    ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9]  = 15; 
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+    ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+    ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand    = 0xff;
+    ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre  = 0;
+    ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+    ibl.bootModes[1].u.nandBoot.nandInfo.postCommand     = FALSE;
+    
+       ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+       ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+       ibl.bootModes[2].port     = ibl_PORT_SWITCH_ALL;
 
-       ibl.bootModes[1].u.ethBoot.doBootp          = FALSE;
-       ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
-       ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
-       ibl.bootModes[1].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_ELF;
+       ibl.bootModes[2].u.ethBoot.doBootp          = FALSE;
+       ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+       ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+       ibl.bootModes[2].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
 
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr,    192,168,1,100);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp,  192,168,1,101);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
-    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask,   255,255,255,0);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr,    192,168,2,100);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp,  192,168,2,101);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask,   255,255,255,0);
 
     /* Use the e-fuse value */
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
-    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
-
-
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0]  = 'a';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1]  = 'p';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2]  = 'p';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3]  = '.';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4]  = 'o';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5]  = 'u';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6]  = 't';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9]  = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
-    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
-
-    ibl.bootModes[1].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
-    ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
-
-       ibl.chkSum = 0;
-}
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+    ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0]  = 'a';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1]  = 'p';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2]  = 'p';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3]  = '.';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4]  = 'o';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5]  = 'u';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6]  = 't';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9]  = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+    ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* 10 MB */
+    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
 
-hotmenu setConfig_c6670_emac()
-{
-    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY+1;
-    ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+    ibl.chkSum = 0;
 }
+