for loop for pll + ddr_ctr_config
authorPrabhu Kuttiyam <pkuttiyam@ti.com>
Thu, 17 Nov 2011 19:12:17 +0000 (14:12 -0500)
committerPrabhu Kuttiyam <pkuttiyam@ti.com>
Thu, 17 Nov 2011 19:12:17 +0000 (14:12 -0500)
src/device/c66x/c66x.c
src/make/ibl_c66x/ibl_objs_template.inc

index 522e760206a6f8339a90b0d8ea3e12b698bf56ce..d511c7de600f86ddef28b4f6a6f11d7522495b14 100644 (file)
@@ -66,6 +66,7 @@
 #include "spi_api.h"
 #include <string.h>
 
+#define PLL_DDR_INIT_LOOPMAX 10
 extern cregister unsigned int DNUM;
 
 /**
@@ -122,12 +123,38 @@ Uint32 deviceLocalAddrToGlobal (Uint32 addr)
  */
 void deviceDdrConfig (void)
 {
+    uint32 loopcount=0;
     /* The emif registers must be made visible. MPAX mapping 2 is used */
     DEVICE_REG_XMPAX_L(2) =  0x10000000 | 0xff;     /* replacement addr + perm*/
     DEVICE_REG_XMPAX_H(2) =  0x2100000B;         /* base addr + seg size (64KB)*/      
-
-    if (ibl.ddrConfig.configDdr != 0)
-        hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+    
+    for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX ; loopcount++)
+    {
+       /* Calling MAIN, PA, DDR PLL init before DDR controller init */
+       if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+               hwPllSetPll (MAIN_PLL, 
+                            ibl.pllConfig[ibl_MAIN_PLL].prediv,
+                             ibl.pllConfig[ibl_MAIN_PLL].mult,
+                             ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+        if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+            hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+                            ibl.pllConfig[ibl_NET_PLL].prediv,
+                            ibl.pllConfig[ibl_NET_PLL].mult,
+                            ibl.pllConfig[ibl_NET_PLL].postdiv,
+                            ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                            ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+
+        if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+            hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+                             ibl.pllConfig[ibl_DDR_PLL].prediv,
+                             ibl.pllConfig[ibl_DDR_PLL].mult,
+                             ibl.pllConfig[ibl_DDR_PLL].postdiv,
+                             ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                             ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+        if (ibl.ddrConfig.configDdr != 0)
+            hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+    }
 
 }
         
index 9e24923a6b0fae7bed444d757e44afd4f77ffa7c..c39b57d1ed4fced5a69e7f8c168a9a34970e6c0a 100644 (file)
@@ -11,6 +11,9 @@
 ../hw/c64x/make/psc.ENDIAN_TAG.oc
 ../hw/c64x/make/emif4.ENDIAN_TAG.oc
 ../device/c64x/make/c64x.ENDIAN_TAG.oa
+../hw/c64x/make/pll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
 
 
 #ifndef EXCLUDE_BIS