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raw | patch | inline | side by side (parent: 4720208)
author | Aravind Batni <aravindbr@ti.com> | |
Wed, 9 May 2012 18:55:51 +0000 (14:55 -0400) | ||
committer | Aravind Batni <aravindbr@ti.com> | |
Wed, 9 May 2012 18:55:51 +0000 (14:55 -0400) |
src/device/c66x/c66x.c | patch | blob | history | |
src/device/c66x/c66xutil.c | [changed mode: 0644->0755] | patch | blob | history |
src/device/c66x/target.h | patch | blob | history |
diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
index 0fcdd99e7628988472d1e4754a262565eab150e7..ba72d9045a489fc06cc7647e70f5c969510da839 100755 (executable)
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
else
{
uart_write_string("IBL: PLL and DDR Initialization Complete",0);
- /* Clear the 16MB DDR3 memory - Workaround - should be removed after Linux fixes the issue */
- ddr3_memory_zero(16);
}
uart_write_string(ddr_result_code_str,0);
#endif
return 0;
}
-
-void ddr3_memory_zero(UINT32 size_mb )
-{
- UINT32 index;
-
- /* clear memory */
- for (index = DDR3_TEST_START_ADDRESS; index < (DDR3_TEST_START_ADDRESS + (size_mb *1024*1024)); index += 4) {
- *(VUint32 *) index = (UINT32)0;
- }
-}
-
#endif
index a89b70c20c2ba71c177f4be6e2db620ad5fa0ad2..560d7968b0a0a40b4aee8c5ef0b4431648ec3fb5 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
#define PLL_REINIT_WORKAROUND
UINT32 ddr3_memory_test();
-void ddr3_memory_zero(UINT32 size_mb );
#endif /* _TARGET_H */