removed clearing of DDR3 initializations in IBL helping NAND boot, after rootcausing...

diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
index 0fcdd99e7628988472d1e4754a262565eab150e7..ba72d9045a489fc06cc7647e70f5c969510da839 100755 (executable)
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
@@ -195,8 +195,6 @@ void deviceDdrConfig (void)
     else
     {
         uart_write_string("IBL: PLL and DDR Initialization Complete",0);
-        /* Clear the 16MB DDR3 memory - Workaround - should be removed after Linux fixes the issue */
-        ddr3_memory_zero(16);
     }
     uart_write_string(ddr_result_code_str,0);
 #endif

diff --git a/src/device/c66x/c66xutil.c b/src/device/c66x/c66xutil.c
old mode 100644 (file)
new mode 100755 (executable)
index 8b61a5d..1e09a5a
--- a/src/device/c66x/c66xutil.c
+++ b/src/device/c66x/c66xutil.c
@@ -173,16 +173,5 @@ UINT32 ddr3_memory_test (void)
 
        return 0;
 }
-
-void ddr3_memory_zero(UINT32 size_mb )
-{
-        UINT32 index;
-
-       /* clear memory */
-       for (index = DDR3_TEST_START_ADDRESS; index < (DDR3_TEST_START_ADDRESS + (size_mb *1024*1024)); index += 4) {
-               *(VUint32 *) index = (UINT32)0;
-       }
-}
-
 #endif
 

diff --git a/src/device/c66x/target.h b/src/device/c66x/target.h
index a89b70c20c2ba71c177f4be6e2db620ad5fa0ad2..560d7968b0a0a40b4aee8c5ef0b4431648ec3fb5 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
@@ -415,6 +415,5 @@ Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
 #define PLL_REINIT_WORKAROUND
 
 UINT32 ddr3_memory_test();
-void ddr3_memory_zero(UINT32 size_mb );
 #endif /* _TARGET_H */