Modified IBL to re-init PLL in DDR controller, added UART

diff --git a/src/device/c64x/make/makefile b/src/device/c64x/make/makefile
index b5fbbc0f61f73643dd196b075d45f3cce939519e..d1af17ad938f5dda31ba7f50691c770018f31979 100644 (file)
--- a/src/device/c64x/make/makefile
+++ b/src/device/c64x/make/makefile
@@ -101,6 +101,7 @@ C6X_C_DIR+= ;$(IBL_ROOT)/hw/nands
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/nors
 C6X_C_DIR+= ;$(IBL_ROOT)/driver/eth
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/spi
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/uart/c66x_uart
 export C6X_C_DIR
 
 vpath % $(IBL_ROOT)/device/$(TARGET)

diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
old mode 100644 (file)
new mode 100755 (executable)
index d511c7d..31fa4a4
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
@@ -65,9 +65,64 @@
 #include "nor_api.h"
 #include "spi_api.h"
 #include <string.h>
+#include <stdint.h>
+#include "evmc66x_uart.h"
 
 #define PLL_DDR_INIT_LOOPMAX 10
 extern cregister unsigned int DNUM;
+#define DDR3_TEST_ENABLE
+
+#ifdef DDR3_TEST_ENABLE
+/**
+ *  @brief Simple DDR3 test
+ *
+ *  @details
+ *      This function performs a simple DDR3 test for a memory range
+ *      specified below and returns -1 for failure and 0 for success.
+ */
+
+#define DDR3_TEST_START_ADDRESS 0x80000000
+
+#define DDR3_TEST_END_ADDRESS   (DDR3_TEST_START_ADDRESS + (128 *1024))
+
+static int32_t ddr3_memory_test (void)
+{
+       uint32_t index, value;
+
+       /* Write a pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+               *(volatile uint32_t *) index = (uint32_t)index;
+       }
+
+       /* Read and check the pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+               value = *(uint32_t *) index;
+
+               if (value  != index) {
+                       return -1;
+               }
+       }
+
+       /* Write a pattern for complementary values */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+               *(volatile uint32_t *) index = (uint32_t)~index;
+       }
+
+       /* Read and check the pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+               value = *(uint32_t *) index;
+
+               if (value  != ~index) {
+                       return -1;
+               }
+       }
+
+       return 0;
+}
+
+#endif
 
 /**
  *  @brief Determine if an address is local
@@ -124,36 +179,59 @@ Uint32 deviceLocalAddrToGlobal (Uint32 addr)
 void deviceDdrConfig (void)
 {
     uint32 loopcount=0;
+    uint32 uartcount=10;
+    int8  ddr_pass_str[20] = "IBL: DDR TEST PASS\n";
+    int8  ddr_fail_str[20] = "IBL: DDR TEST FAIL\n";
+    int8  ibl_msg_str1[20] = "IBL: PLL SEQ DONE \n";
+       
+               
     /* The emif registers must be made visible. MPAX mapping 2 is used */
     DEVICE_REG_XMPAX_L(2) =  0x10000000 | 0xff;     /* replacement addr + perm*/
     DEVICE_REG_XMPAX_H(2) =  0x2100000B;         /* base addr + seg size (64KB)*/      
     
     for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX ; loopcount++)
     {
-       /* Calling MAIN, PA, DDR PLL init before DDR controller init */
-       if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
-               hwPllSetPll (MAIN_PLL, 
-                            ibl.pllConfig[ibl_MAIN_PLL].prediv,
-                             ibl.pllConfig[ibl_MAIN_PLL].mult,
-                             ibl.pllConfig[ibl_MAIN_PLL].postdiv);
-
-        if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
-            hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
-                            ibl.pllConfig[ibl_NET_PLL].prediv,
-                            ibl.pllConfig[ibl_NET_PLL].mult,
-                            ibl.pllConfig[ibl_NET_PLL].postdiv,
-                            ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
-                            ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
-
-        if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
-            hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
-                             ibl.pllConfig[ibl_DDR_PLL].prediv,
-                             ibl.pllConfig[ibl_DDR_PLL].mult,
-                             ibl.pllConfig[ibl_DDR_PLL].postdiv,
-                             ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
-                             ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+        if(loopcount !=0) /*Do not call PLL sequence for the first time */
+        {
+       /* Calling MAIN, PA, DDR PLL init  */
+           if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+               hwPllSetPll (MAIN_PLL, 
+                            ibl.pllConfig[ibl_MAIN_PLL].prediv,
+                                 ibl.pllConfig[ibl_MAIN_PLL].mult,
+                                 ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+    
+            if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+                hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+                                ibl.pllConfig[ibl_NET_PLL].prediv,
+                                ibl.pllConfig[ibl_NET_PLL].mult,
+                                ibl.pllConfig[ibl_NET_PLL].postdiv,
+                                ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                                ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+    
+            if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+                hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+                                 ibl.pllConfig[ibl_DDR_PLL].prediv,
+                                 ibl.pllConfig[ibl_DDR_PLL].mult,
+                                 ibl.pllConfig[ibl_DDR_PLL].postdiv,
+                                 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                                 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+         }
+         
         if (ibl.ddrConfig.configDdr != 0)
             hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+        /* Init UART */
+        uart_init();
+        /* Write something to UART */
+          uart_write_string(ibl_msg_str1,19);
+#ifdef DDR3_TEST_ENABLE
+       if (ddr3_memory_test() == 0) 
+       {
+           uart_write_string(ddr_pass_str,19);
+           break;
+       }
+#endif
+      uart_write_string(ddr_fail_str,19);
+
     }
 
 }

diff --git a/src/hw/c64x/make/makefile b/src/hw/c64x/make/makefile
index 6b267fb19a8e2d3bdcf301d41f080b865ad9eb81..86910102dd5a8fe517d99909e2b5fe3e7b074a12 100644 (file)
--- a/src/hw/c64x/make/makefile
+++ b/src/hw/c64x/make/makefile
@@ -64,7 +64,7 @@ else
        else
         ifeq ($(TARGET),c66x)
          CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c cpsw.c qm.c cpdma.c pa.c sgmii.c serdes.c gmacsl.c emif4.c gpio.c
-         CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
+         CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c evmc66x_uart.c
      else
       CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c cfgpll.c cfgpll2.c
          CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
@@ -194,6 +194,7 @@ ifeq ($(TARGET),c66x)
  vpath % $(ECODIR)/nors/emif25
  vpath % $(ECODIR)/nors/spi
  vpath % $(ECODIR)/emif25
+ vpath % $(ECODIR)/uart/c66x_uart
 endif
 
 

diff --git a/src/hw/uart/c66x_uart/evmc66x_uart.c b/src/hw/uart/c66x_uart/evmc66x_uart.c
old mode 100644 (file)
new mode 100755 (executable)
index 7d319bb..639e130
--- a/src/hw/uart/c66x_uart/evmc66x_uart.c
+++ b/src/hw/uart/c66x_uart/evmc66x_uart.c
@@ -1,124 +1,95 @@
 /******************************************************************************
  * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
- * 
- *  Redistribution and use in source and binary forms, with or without 
- *  modification, are permitted provided that the following conditions 
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
  *  are met:
  *
- *    Redistributions of source code must retain the above copyright 
+ *    Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  *
  *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the   
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
  *    distribution.
  *
  *    Neither the name of Texas Instruments Incorporated nor the names of
  *    its contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
  *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  *****************************************************************************/
 
-#include "platform_internal.h"
-
-#if (PLATFORM_UART_IN)
-
-/******************************************************************************
- *
- * File Name:          evmc66x_uart.c
- *
- * Description:        This file contains APIs for  UART. 
- * 
- * 
- ******************************************************************************/
+#include "evmc66x_uart.h"
 
-/************************
- * Include Files
- ************************/
+static void uart_delay_cycles(uint32_t cycles)
+{
+       while (cycles--) {
+               asm ("NOP");
+       }
+}
 
-/******************************************************************************
- * 
- * Function:   UartInit  
- *
- * Description:        This function initializes the UART. 
- *
- * Parameters: void
- *
- * Return Value: void
- * 
- ******************************************************************************/
-void UartInit(void)
+void uart_init(void)
 {
-    //      Allows access to the divisor latches of the baud generator during a 
+       uint16_t uiBaudRate;
+    uint8_t uiDLLVal = 0;
+    uint8_t uiDLHVal = 0;
+
+    // Allows access to the divisor latches of the baud generator during a
     // read or write operation (DLL and DLH)
-    CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
-    //      Break condition is disabled.
-    CSL_FINS (hUartRegs->LCR, UART_LCR_BC,   CSL_UART_LCR_BC_DISABLE);
-    //      Stick parity is disabled.
-    CSL_FINS (hUartRegs->LCR, UART_LCR_SP,   CSL_UART_LCR_SP_DISABLE);
-    //      Odd parity is selected
-    CSL_FINS (hUartRegs->LCR, UART_LCR_EPS,  CSL_UART_LCR_EPS_ODD);
-    //      No PARITY bit is transmitted or checked
-    CSL_FINS (hUartRegs->LCR, UART_LCR_PEN,  CSL_UART_LCR_PEN_DISABLE);    
 
-    // Set the baudrate,for accessing LCR[7] should be enable 
+    hUartRegs->LCR = 0x80;
+
+    // Set the baudrate,for accessing LCR[7] should be enable
     hUartRegs->DLL  = DLL_VAL;
     hUartRegs->DLH  = DLM_VAL;
 
-    // Allows access to the receiver buffer register (RBR), 
+    // Allows access to the receiver buffer register (RBR),
     // the transmitter holding register (THR), and the
     // interrupt enable register (IER) selected.
-    CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_DISABLE);
-    // Even Parity is selected
-    CSL_FINS (hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_EVEN);
-    // Parity Enable 
-    CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_ENABLE);
- 
+    hUartRegs->LCR = 0x18;
+
     // Disable THR, RHR, Receiver line status interrupts
-    CSL_FINS (hUartRegs->IER, UART_IER_ERBI,  CSL_UART_IER_ERBI_DISABLE);
-    CSL_FINS (hUartRegs->IER, UART_IER_ETBEI, CSL_UART_IER_ETBEI_DISABLE);
-    CSL_FINS (hUartRegs->IER, UART_IER_ELSI,  CSL_UART_IER_ELSI_DISABLE);
-    CSL_FINS (hUartRegs->IER, UART_IER_EDSSI, CSL_UART_IER_EDSSI_DISABLE);  
+    hUartRegs->IER = 0;
 
-    /* If autoflow control is desired, 
-    * write appropriate values to the modem 
-    * control register (MCR). Note that all UARTs 
-    * do not support autoflow control, see 
+    /* If autoflow control is desired,
+    * write appropriate values to the modem
+    * control register (MCR). Note that all UARTs
+    * do not support autoflow control, see
     * the device-specific data manual for supported features.
-    * 
+    *
     * MCR
     * ====================================================
     * Bit  Field   Value   Description
     * 5    AFE     0       Autoflow control is disabled
     * 4    LOOP    0       Loop back mode is disabled.
-    * 1    RTS     0       RTS control (UARTn_RTS is disabled, 
+    * 1    RTS     0       RTS control (UARTn_RTS is disabled,
     *                      UARTn_CTS is only enabled.)
     * =====================================================
-    * 
-    * 
+    *
+    *
     */
 
     hUartRegs->MCR = 0;
 
-    /* Choose the desired response to 
-    * emulation suspend events by configuring 
-    * the FREE bit and enable the UART by setting 
-    * the UTRST and URRST bits in the power and 
+    /* Choose the desired response to
+    * emulation suspend events by configuring
+    * the FREE bit and enable the UART by setting
+    * the UTRST and URRST bits in the power and
     * emulation management register (PWREMU_MGMT).
-    * 
-    * 
+    *
+    *
     * PWREMU_MGMT
     * =================================================
     * Bit  Field   Value   Description
@@ -126,133 +97,66 @@ void UartInit(void)
     * 13   URRST   1       Receiver is enabled
     * 0    FREE    1       Free-running mode is enabled
     * ===================================================
-    * 
+    *
     */
     hUartRegs->PWREMU_MGMT = 0x6001;
 
     /* Cleanup previous data (rx trigger is also set to 0)*/
     /* Set FCR = 0x07;        */
-    CSL_FINS (hUartRegs->FCR, UART_FCR_FIFOEN,   CSL_UART_FCR_FIFOEN_ENABLE);
-    CSL_FINS (hUartRegs->FCR, UART_FCR_TXCLR,    CSL_UART_FCR_TXCLR_CLR);
-    CSL_FINS (hUartRegs->FCR, UART_FCR_RXCLR,    CSL_UART_FCR_RXCLR_CLR);
-    CSL_FINS (hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
-    CSL_FINS (hUartRegs->FCR, UART_FCR_RXFIFTL,  CSL_UART_FCR_RXFIFTL_CHAR1);
+    hUartRegs->FCR = 0xC1;
 
-    return;
-}
-
-/******************************************************************************
- * 
- * Function:   UartSetBaudRate  
- *
- * Description:        This function sets the UART baudrate. 
- *
- * Parameters: UINT16 uiBaudRate - baudrate to set
- *
- * Return Value: void
- * 
- ******************************************************************************/
-void UartSetBaudRate(uint16_t uiBaudRate)
-{
-    uint8_t uiDLLVal = 0;
-    uint8_t uiDLHVal = 0;
+    /* Setting baud rate to 115200 */
+    uiBaudRate = 88;
 
+    /* Setting the baud rate */
     hUartRegs->LCR = 0x80;
     uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
     uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate  >> 8));
 
-    // Set the baudrate,for accessing LCR[7] should be enable 
+    // Set the baudrate,for accessing LCR[7] should be enable
     hUartRegs->DLL  = uiDLLVal;
     hUartRegs->DLH  = uiDLHVal;
-    hUartRegs->LCR = 0x03;
-}
-
-/******************************************************************************
- * 
- * Function:   UartReadBaudRate  
- *
- * Description:        This function reads the UART baudrate. 
- *
- * Parameters: UART_device eUartDevice - Uart Device
- *
- * Return Value: UINT16 - 16 bit Baudrate read from UART
- * 
- ******************************************************************************/
-uint16_t UartReadBaudRate(void)
-{
-    uint16_t ushBaudrate = 0;
-    uint16_t ushTemp = 0;
+    hUartRegs->LCR  = 0x03;
 
     hUartRegs->LCR = 0x80;
-    // Read the baudrate 
-    ushBaudrate = hUartRegs->DLL;
-    ushTemp     = hUartRegs->DLH;
-    ushBaudrate = (ushBaudrate & 0xFF) | ((ushTemp & 0xFF) << 8); 
+    uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
+    uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate  >> 8));
+    // Set the baudrate,for accessing LCR[7] should be enable
+    hUartRegs->DLL  = uiDLLVal;
+    hUartRegs->DLH  = uiDLHVal;
     hUartRegs->LCR = 0x03;
-    return ushBaudrate;
-}
 
-/******************************************************************************
- * 
- * Function:   UartReadData  
- *
- * Description: This function reads a byte of data from I2C UART device  
- * 
- * Return Value: uint8_t - 8-bit value read from the RBR register
- ******************************************************************************/
-uint8_t UartReadData(void)
-{
-       uint8_t uRcvChar = 0;
-       
-       uRcvChar = CSL_FEXT(hUartRegs->RBR, UART_RBR_DATA);
-       
-       return uRcvChar;
+    return;
 }
 
 /******************************************************************************
- * 
- * Function:   UartWriteData
  *
- * Description:        This function writes a byte of data to UART device  
- * 
+ * Function:   uart_write_byte
+ *
+ * Description:        This function writes a byte of data to UART device
+ *
  * Parameters: uint8_t uchAddress - Address of 8-bit register
  *                             uint8_t uchByte -  8-bit data to write to THR
  *
  * Return Value: none
  ******************************************************************************/
-void UartWriteData(uint8_t uchByte)
-
+static void uart_write_byte(uint8_t uchByte)
 {
-    while (!(CSL_FEXT(hUartRegs->LSR, UART_LSR_THRE))) {
-               platform_delaycycles(10000);
+    while (!(hUartRegs->LSR & UART_LSR_THRE_MASK)) {
+       uart_delay_cycles(10000);
     }
-    CSL_FINS(hUartRegs->THR, UART_THR_DATA, uchByte);
+    hUartRegs->THR = (UART_THR_DATA_MASK & uchByte);
     return;
 }
 
-
-
-/******************************************************************************
- * 
- * Function:   UartIsDataReady
- *
- * Description:        This function gets the status of DR bit  
- * 
- * Parameters: none
- * 
- * Return Value: Status of DR bit
- *                             
- ******************************************************************************/
-Bool UartIsDataReady(void)
+void uart_write_string(uint8_t * str, uint32_t length)
 {
-       Bool DR_val = FALSE;
-       
-       if (CSL_UART_LSR_DR_READY == (CSL_FEXT(hUartRegs->LSR, UART_LSR_DR))) {
-        DR_val  = TRUE;
-    }
-       
-       return (DR_val);
+       uint32_t i;
+       uart_write_byte((uint8_t)0x0D);
+       uart_write_byte((uint8_t)0x0A);
+       for(i = 0; i < length; i++)
+       {
+               uart_write_byte(str[i]);
+       }
 }
-/* Nothing past this point */
 
-#endif

diff --git a/src/hw/uart/c66x_uart/evmc66x_uart.h b/src/hw/uart/c66x_uart/evmc66x_uart.h
old mode 100644 (file)
new mode 100755 (executable)
index 1efe606..a638eaf
--- a/src/hw/uart/c66x_uart/evmc66x_uart.h
+++ b/src/hw/uart/c66x_uart/evmc66x_uart.h
@@ -1,37 +1,37 @@
 /******************************************************************************
  * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
- * 
- *  Redistribution and use in source and binary forms, with or without 
- *  modification, are permitted provided that the following conditions 
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
  *  are met:
  *
- *    Redistributions of source code must retain the above copyright 
+ *    Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  *
  *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the   
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
  *    distribution.
  *
  *    Neither the name of Texas Instruments Incorporated nor the names of
  *    its contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
  *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  *****************************************************************************/
- 
-/******************************************************************************        
+
+/******************************************************************************
  *
  * File        Name:   evmc66x_i2c_uart.h
  *
@@ -41,34 +41,58 @@
  ******************************************************************************/
 #ifndef        _EVM66X_I2C_UART_H_
 #define        _EVM66X_I2C_UART_H_
+#include <stdint.h>
+
+#define UART_REGS_BASE            (0x02540000)
+
+/**************************************************************************\
+* Register Overlay Structure
+\**************************************************************************/
+typedef struct  {
+    volatile uint32_t RBR;
+    volatile uint32_t IER;
+    volatile uint32_t IIR;
+    volatile uint32_t LCR;
+    volatile uint32_t MCR;
+    volatile uint32_t LSR;
+    volatile uint32_t MSR;
+    volatile uint32_t SCR;
+    volatile uint32_t DLL;
+    volatile uint32_t DLH;
+    volatile uint32_t REVID1;
+    volatile uint32_t REVID2;
+    volatile uint32_t PWREMU_MGMT;
+    volatile uint32_t MDR;
+} UartRegs;
 
 /************************
  * Defines and Macros
  ************************/
-// Mask        to enable DLL and DLM
+/* Mask        to enable DLL and DLM */
 #define        DLAB            (0x80)                  // Way to swap mem banks
 
-// for 19200 baudrate for crystal clock        14.7456 MHz
+/* for 19200 baudrate for crystal clock        14.7456 MHz*/
 #define        DLL_VAL         (0x30)
 #define        DLM_VAL         (0x00)
 
-// Macros to be        used for setting baudrate
+/* Macros to be        used for setting baudrate */
 #define        BAUD_RATE_9600          (0x0060)
 #define        BAUD_RATE_19200         (0x0030)
 #define        BAUD_RATE_56000         (0x0010)
 #define        BAUD_RATE_115200        (0x0008)
 
-#define hUartRegs    ((CSL_UartRegs*) CSL_UART_REGS)
+#define hUartRegs    ((UartRegs*) UART_REGS_BASE)
 
+/* Following 2 lines are added due to CSL3.x tools limitations */
+#define THR RBR   /* RBR & THR have same offset */
+#define FCR IIR   /* IIR & FCR have same offset */
+
+#define UART_LSR_THRE_MASK (0x00000020u)
+#define UART_THR_DATA_MASK (0x000000FFu)
 
 /************************
  * Function declarations
 ************************/
-void UartInit(void);
-void UartSetBaudRate(uint16_t uiBaudRate);
-uint16_t UartReadBaudRate(void);
-uint8_t UartReadData(void);
-void UartWriteData(uint8_t uchByte);
-Bool UartIsDataReady(void);
-#endif // _EVM66X_I2C_UART_H_
-
+void uart_init(void);
+void uart_write_string(uint8_t * str, uint32_t length);
+#endif /* _EVM66X_I2C_UART_H_ */

diff --git a/src/main/c64x/make/makefile b/src/main/c64x/make/makefile
index 0d29e1a35a0d5642e8e2edaddad09bd899e2ea5c..b546c601ed3224e1e22b5994988dafcf69fffa84 100644 (file)
--- a/src/main/c64x/make/makefile
+++ b/src/main/c64x/make/makefile
@@ -74,6 +74,7 @@ C6X_C_DIR+= ;$(IBL_ROOT)/nandboot
 C6X_C_DIR+= ;$(IBL_ROOT)/norboot
 C6X_C_DIR+= ;$(IBL_ROOT)/driver/timer
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/i2c
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/uart/c66x_uart
 C6X_C_DIR+= ;$(IBL_ROOT)/hw/spi
 C6X_C_DIR+= ;$(IBL_ROOT)/cfg/$(TARGET)
 C6X_C_DIR+= ;$(STDINC)

diff --git a/src/main/iblmain.c b/src/main/iblmain.c
old mode 100644 (file)
new mode 100755 (executable)

diff --git a/src/make/ibl_c66x/ibl_objs_template.inc b/src/make/ibl_c66x/ibl_objs_template.inc
index c39b57d1ed4fced5a69e7f8c168a9a34970e6c0a..1d6a7b36d2422a644df55977ce402dc48cb94191 100644 (file)
--- a/src/make/ibl_c66x/ibl_objs_template.inc
+++ b/src/make/ibl_c66x/ibl_objs_template.inc
@@ -14,7 +14,7 @@
 ../hw/c64x/make/pll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
-
+../hw/c64x/make/evmc66x_uart.ENDIAN_TAG.oc
 
 #ifndef EXCLUDE_BIS
 ../interp/c64x/make/bis.ENDIAN_TAG.oc