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raw | patch | inline | side by side (parent: 86f576a)
raw | patch | inline | side by side (parent: 86f576a)
author | Sandeep Paulraj <s-paulraj@ti.com> | |
Fri, 4 Nov 2011 17:34:22 +0000 (13:34 -0400) | ||
committer | Sandeep Paulraj <s-paulraj@ti.com> | |
Fri, 4 Nov 2011 17:34:22 +0000 (13:34 -0400) |
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/device/c66x/c66xinit.c | patch | blob | history |
index c46e9eaa1b017a3351e8a562180811180829fe8e..a9d72a0e36ae72426463f2e11630efc19a0b05a0 100644 (file)
#include "tiboot_c66x.h"
#include "tiboot_c66x.h"
+#define CHIP_LEVEL_REG 0x02620000
+#define DDR3PLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
+#define DDR3PLLCTL1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0334)
+
+static void ddr3_delay (uint32 del)
+{
+ volatile unsigned int i;
+
+ for (i = 0; i < del; i++);
+
+}
+
/**
* @brief Configure the PLLs
*
/**
* @brief Configure the PLLs
*
*/
void devicePllConfig (void)
{
*/
void devicePllConfig (void)
{
+ unsigned int i;
/* Unlock the chip registers and leave them unlocked */
*((Uint32 *)0x2620038) = 0x83e70b13;
/* Unlock the chip registers and leave them unlocked */
*((Uint32 *)0x2620038) = 0x83e70b13;
ibl.pllConfig[ibl_MAIN_PLL].mult,
ibl.pllConfig[ibl_MAIN_PLL].postdiv);
ibl.pllConfig[ibl_MAIN_PLL].mult,
ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+
+ /* 1333 MHz data rate */
+ /***************** 2.2 DDR3 PLL Configuration ************/
+ DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
+ DDR3PLLCTL0 |= 0x00800000; // Set BYPASS = 1
+ DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
+
+ DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ
+
+ for (i = 0;i < 20;i++)
+ ddr3_delay(1000); //Wait for reset to complete
+
+ DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit
+
+ for (i = 0;i < 500;i++)
+ ddr3_delay(1000); //Wait for PLL lock
+
+ DDR3PLLCTL0 &= ~(0x00800000); // Set BYPASS = 0
+
+#if 0
+
if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
ibl.pllConfig[ibl_DDR_PLL].prediv,
if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
ibl.pllConfig[ibl_DDR_PLL].prediv,
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+#endif
+
if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
ibl.pllConfig[ibl_NET_PLL].prediv,
if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
ibl.pllConfig[ibl_NET_PLL].prediv,