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raw | patch | inline | side by side (parent: ffd29fd)
raw | patch | inline | side by side (parent: ffd29fd)
Clean up the code and fixed instablitily issue in the NAND/EMIF driver DEV.MCSDK.02.00.00.IBL.NAND_BOOT_CLEANUP
author | Hao Zhang <hzhang@ti.com> | |
Sun, 6 Mar 2011 15:40:51 +0000 (10:40 -0500) | ||
committer | Hao Zhang <hzhang@ti.com> | |
Sun, 6 Mar 2011 15:40:51 +0000 (10:40 -0500) |
index 195e77d68b5b1209a32e0d0477280c051ad58854..28036955a53499013871392019e1b29838b78b8b 100644 (file)
dev_stat = DEVICE_REG32_R(DEVICE_REG_DEVSTAT );
dev_stat &= ~(0x0000080E);
dev_stat |= ((bm_hi << 8) | bm_lo);
dev_stat = DEVICE_REG32_R(DEVICE_REG_DEVSTAT );
dev_stat &= ~(0x0000080E);
dev_stat |= ((bm_hi << 8) | bm_lo);
-#if 0
- /* Unlock Boot Config */
- *((volatile Uint32 *)0x2620038) = 0x83e70b13;
- *((volatile Uint32 *)0x262003c) = 0x95a4f1e0;
-#endif
/* Update the DEVSTAT register for the intended Boot Device and i2c Addr */
DEVICE_REG32_W (DEVICE_REG_DEVSTAT, dev_stat);
/* Update the DEVSTAT register for the intended Boot Device and i2c Addr */
DEVICE_REG32_W (DEVICE_REG_DEVSTAT, dev_stat);
-#if 0
- /* Lock Boot Config */
- *((volatile Uint32 *)0x2620038) = 0;
- *((volatile Uint32 *)0x262003c) = 0;
-#endif
+
exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
(*exit)();
}
exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
(*exit)();
}
index caceb60fc6ff2595bce3946250a5b81e94d78f37..fdcf9683ec4c1151cde827191ab7cf9724f4aec5 100644 (file)
#define NAND_ALE_OFFSET 0x2000 /* Address latch enable register offset */
#define NAND_CMD_OFFSET 0x4000 /* Command latch enable register offset */
#define NAND_ALE_OFFSET 0x2000 /* Address latch enable register offset */
#define NAND_CMD_OFFSET 0x4000 /* Command latch enable register offset */
-#define NAND_DELAY 50000
+#define NAND_DELAY 50000
+
+#define DEVICE_REG8_W(x,y) *(volatile Uint8 *)(x)=(y)
+#define DEVICE_REG8_R(x) (*(volatile Uint8 *)(x))
+
+#define DEVICE_REG16_W(x,y) *(volatile Uint16 *)(x)=(y)
+#define DEVICE_REG16_R(x) (*(volatile Uint16 *)(x))
extern void chipDelay32 (uint32 del);
extern uint32 deviceEmif25MemBase (int32 cs);
extern void chipDelay32 (uint32 del);
extern uint32 deviceEmif25MemBase (int32 cs);
Uint32 addr
)
{
Uint32 addr
)
{
- DEVICE_REG32_W (memBase + NAND_ALE_OFFSET, addr);
+ DEVICE_REG8_W (memBase + NAND_ALE_OFFSET, addr);
}
void
}
void
Uint32 cmd
)
{
Uint32 cmd
)
{
- DEVICE_REG32_W (memBase + NAND_CMD_OFFSET, cmd);
+ DEVICE_REG8_W (memBase + NAND_CMD_OFFSET, cmd);
}
void
}
void
)
{
Int32 i;
)
{
Int32 i;
+ Uint16 *data16;
if (hwDevInfo->busWidthBits == 8)
{
for (i = 0; i < nbytes; i++)
if (hwDevInfo->busWidthBits == 8)
{
for (i = 0; i < nbytes; i++)
- data[i] = *(volatile Uint8 *)memBase;
+ data[i] = DEVICE_REG8_R(memBase);
- } else {
+ }
+ else
+ {
+ data16 = (Uint16 *)data;
for (i = 0; i < (nbytes+1) >> 1; i++)
for (i = 0; i < (nbytes+1) >> 1; i++)
- data[i] = *(volatile Uint16 *)memBase;
+ data16[i] = DEVICE_REG16_R(memBase);
}
}
}
}
hwDevInfo = (nandDevInfo_t *)vdevInfo;
memBase = deviceEmif25MemBase (cs);
hwDevInfo = (nandDevInfo_t *)vdevInfo;
memBase = deviceEmif25MemBase (cs);
+ nandCmdSet(hwDevInfo->resetCommand);
+ chipDelay32 (NAND_DELAY);
+
return (0);
}
return (0);
}
@@ -118,19 +131,7 @@ Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32
addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset) | ((byte & 0xff) << hwDevInfo->columnOffset);
addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset) | ((byte & 0xff) << hwDevInfo->columnOffset);
- if (byte < 256)
- {
- cmd = hwDevInfo->readCommandPre;
- }
- else if (byte < 512)
- {
- cmd = hwDevInfo->readCommandPre + 1;
- }
- else
- {
- cmd = 0x50;
- }
-
+ cmd = hwDevInfo->readCommandPre;
nandCmdSet(cmd); // First cycle send 0
/* 4 address cycles */
nandCmdSet(cmd); // First cycle send 0
/* 4 address cycles */
diff --git a/src/ibl.h b/src/ibl.h
index 1d25d2711035546061bf75c628f7c08c757631b9..35b6db501f419698c08100b75d715c9abd1961e6 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
* @brief
* The version number, 1.0.0.0
*/
* @brief
* The version number, 1.0.0.0
*/
-#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,0)
+#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,1)
/**
/**
diff --git a/src/main/iblinit.c b/src/main/iblinit.c
index 65592510db4cbe33f8e0b91057edfb931968a193..5b5642f300df5ee56235c6dc00375d620ed975dc 100644 (file)
--- a/src/main/iblinit.c
+++ b/src/main/iblinit.c
iblStatus.iblVersion = ibl_VERSION;
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_I2C;
iblStatus.iblVersion = ibl_VERSION;
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_I2C;
- /* Pll configuration is device specific */
- devicePllConfig ();
/* Determine the boot device to read from */
bootDevice = deviceReadBootDevice();
/* Determine the boot device to read from */
bootDevice = deviceReadBootDevice();
}
}
+ /* Pll configuration is device specific */
+ devicePllConfig ();
+
/* Enable the EDC for local memory */
if (IBL_ENABLE_EDC)
{
/* Enable the EDC for local memory */
if (IBL_ENABLE_EDC)
{
diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 9731c1b28b7a01cb530fda59aca7015e68a26024..3bcac31e9f124cebcf0983467529e146f858db7b 100644 (file)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
break;
#endif
break;
#endif
- //#if (!defined(EXCLUDE_NAND_EMIF) && !defined(EXCLUDE_NAND_SPI) && !defined(EXCLUDE_NAND_GPIO))
#if ((!defined(EXCLUDE_NAND_EMIF)) )
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
#if ((!defined(EXCLUDE_NAND_EMIF)) )
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
index 7962e2b6a3b1b29187e892c2b5375d77957c89a5..41dc182b1dee0cab3fdeb272c22286d38630a7ca 100644 (file)
deviceConfigureForNand();
/* Initialize the programming interface */
deviceConfigureForNand();
/* Initialize the programming interface */
- ret = nandHwDriverInit (&devInfo);
+ ret = nandHwEmifDriverInit (&devInfo);
if (ret != 0) {
printf ("nandHwDriverInit failed with error code %d\n", ret);
free (data);
if (ret != 0) {
printf ("nandHwDriverInit failed with error code %d\n", ret);
free (data);