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raw | patch | inline | side by side (parent: d173fc1)
raw | patch | inline | side by side (parent: d173fc1)
Corrected PCIE_BAR2 value for 6657; corrected DDR leveling value for 6657 DEV.MAD_UTILS.IBL.01.00.00.15
author | Ivan Pang <i-pang@ti.com> | |
Mon, 21 May 2012 00:45:04 +0000 (20:45 -0400) | ||
committer | Ivan Pang <i-pang@ti.com> | |
Mon, 21 May 2012 00:45:04 +0000 (20:45 -0400) |
src/device/c665x/c665xinit.c | patch | blob | history | |
src/hw/ddrs/emif4/emif4.c | patch | blob | history |
index f0b946b6491bde2ef7c8577e9f5451bed6dede17..6762fc918a5964a27f19d9e71fc83d1ba2e48128 100644 (file)
/* 6657 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00000FFF); /* 4K */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x000FFFFF); /* 1M */
/* 6657 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00000FFF); /* 4K */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x000FFFFF); /* 1M */
- DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x001FFFFF); /* 2M */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x000FFFFF); /* 1M */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x00FFFFFF); /* 16M */
}
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0); /* dbi_cs2=0 */
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x00FFFFFF); /* 16M */
}
DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0); /* dbi_cs2=0 */
index 1e6a18dad35597974ed167c6f41e36d83ba61ae6..379955a63f1480dfa51ce5ca23ef6cd3cb5bdc2b 100755 (executable)
DATA5_WRLVL_INIT_RATIO = 0x3A;
DATA6_WRLVL_INIT_RATIO = 0x2C;
DATA7_WRLVL_INIT_RATIO = 0x2C;
DATA5_WRLVL_INIT_RATIO = 0x3A;
DATA6_WRLVL_INIT_RATIO = 0x2C;
DATA7_WRLVL_INIT_RATIO = 0x2C;
- DATA8_WRLVL_INIT_RATIO = 0x1C;
+ DATA8_WRLVL_INIT_RATIO = 0x21;
DATA0_GTLVL_INIT_RATIO = 0x00;
DATA1_GTLVL_INIT_RATIO = 0x00;
DATA0_GTLVL_INIT_RATIO = 0x00;
DATA1_GTLVL_INIT_RATIO = 0x00;