DDR configuration changes for C6670
authorSandeep Nair <a0875039@gt48xvq51.gt.design.ti.com>
Fri, 15 Apr 2011 18:44:43 +0000 (14:44 -0400)
committerBill Mills <wmills@ti.com>
Mon, 9 May 2011 17:21:40 +0000 (13:21 -0400)
src/hw/ddrs/emif4/emif4.c
src/util/i2cConfig/i2cConfig.gel

index a170814e53e0cb1436160a19d618b3e8a1572fba..39c1904fd8f323558237a550ec78faa5db1596c2 100644 (file)
@@ -18,6 +18,7 @@
 #define KICK1                  *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
 
 #define DDR3PLLCTL0            *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
+#define DDR3PLLCTL1            *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
 
 // DDR3 definitions
 #define DDR_BASE_ADDR 0x21000000
 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
 
+#define RD_DQS_SLAVE_RATIO 0x34
+#define WR_DQS_SLAVE_RATIO 0xA9
+#define WR_DATA_SLAVE_RATIO 0xE9
+#define FIFO_WE_SLAVE_RATIO 0x106
+
 /*************************************************************************************************
  * FUNCTION PUROPSE: Initial EMIF4 setup
  *************************************************************************************************
@@ -66,7 +72,7 @@
  *************************************************************************************************/
 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
 {
-    UINT32 v;
+    UINT32 v, i;
 
 #if 0
     /* If the config registers or refresh control registers are being written
@@ -146,78 +152,116 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0) 
+    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
 
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0) 
+    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
 
     v = cfg->sdRamRefreshCtl;
     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 #endif
-    KICK0 = 0x83E70B13;
-    KICK1 = 0x95A4F1E0;
-    
-    DDR3PLLCTL0 = 0x100807C1;
-
-    DDR_SDTIM1   = 0x0CCF369B;
-    DDR_SDTIM2   = 0x3A3F7FDA;
-    DDR_SDTIM3   = 0x057F83A8;
-    DDR_PMCTL   |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
-   
-    DDR_DDRPHYC  = 0x0010010B;
-   
-    DDR_SDRFC = 0x00004111; //500us
-
-    
-    DDR_SDCFG    = 0x63C51A32; //0x63C51A32;    //row-col = 13-10
-   
-       
-       //Values with invertclkout = 0
-       DATA0_GTLVL_INIT_RATIO = 0x3C;
-       DATA1_GTLVL_INIT_RATIO = 0x3C;
-       DATA2_GTLVL_INIT_RATIO = 0x23;
-       DATA3_GTLVL_INIT_RATIO = 0x2D;
-       DATA4_GTLVL_INIT_RATIO = 0x13;
-       DATA5_GTLVL_INIT_RATIO = 0x11;
-       DATA6_GTLVL_INIT_RATIO = 0x9;
-       DATA7_GTLVL_INIT_RATIO = 0xC;
-       //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
-       
-       //Values with invertclkout = 0  
-       RDWR_INIT_RATIO_0 = 0x0;
-       RDWR_INIT_RATIO_1 = 0x0;
-       RDWR_INIT_RATIO_2 = 0x0;
-       RDWR_INIT_RATIO_3 = 0x0;
-       RDWR_INIT_RATIO_4 = 0x0;
-       RDWR_INIT_RATIO_5 = 0x0;
-       RDWR_INIT_RATIO_6 = 0x0;
-       RDWR_INIT_RATIO_7 = 0x0;
-       //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
-       
-       
-       
-       //GEL_TextOut("\nProgrammed initial ratios.\n");
-       
-       DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
-       
-       //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
-
-       DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
-       //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
-
-       DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
-    DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value                                                        //(0x34) instead
-       //GEL_TextOut("\n Triggered full leveling.\n");
-
-       DDR_SDTIM1; //Read MMR to ensure full leveling is complete
-    
-       DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
-       
+
+    v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+
+    /*KICK0 = 0x83E70B13;
+    KICK1 = 0x95A4F1E0;*/
+
+    if (v == DEVICE_C6618_JTAG_ID_VAL)
+    {
+        DDR3PLLCTL0 = 0x100807C1;
+        
+        DDR_SDTIM1   = 0x0CCF369B;
+        DDR_SDTIM2   = 0x3A3F7FDA;
+        DDR_SDTIM3   = 0x057F83A8;
+        DDR_PMCTL   |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
+        
+        DDR_DDRPHYC  = 0x0010010B;
+        
+        DDR_SDRFC = 0x00004111; //500us
+        
+        
+        DDR_SDCFG    = 0x63C51A32; //0x63C51A32;    //row-col = 13-10
+        
+        
+        //Values with invertclkout = 0
+        DATA0_GTLVL_INIT_RATIO = 0x3C;
+        DATA1_GTLVL_INIT_RATIO = 0x3C;
+        DATA2_GTLVL_INIT_RATIO = 0x23;
+        DATA3_GTLVL_INIT_RATIO = 0x2D;
+        DATA4_GTLVL_INIT_RATIO = 0x13;
+        DATA5_GTLVL_INIT_RATIO = 0x11;
+        DATA6_GTLVL_INIT_RATIO = 0x9;
+        DATA7_GTLVL_INIT_RATIO = 0xC;
+        //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
+        
+        //Values with invertclkout = 0
+        RDWR_INIT_RATIO_0 = 0x0;
+        RDWR_INIT_RATIO_1 = 0x0;
+        RDWR_INIT_RATIO_2 = 0x0;
+        RDWR_INIT_RATIO_3 = 0x0;
+        RDWR_INIT_RATIO_4 = 0x0;
+        RDWR_INIT_RATIO_5 = 0x0;
+        RDWR_INIT_RATIO_6 = 0x0;
+        RDWR_INIT_RATIO_7 = 0x0;
+        //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
+        
+        
+        
+        //GEL_TextOut("\nProgrammed initial ratios.\n");
+        
+        DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
+        
+        //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
+        
+        DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
+        //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
+        
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
+        DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value                                                    //(0x34) instead
+        //GEL_TextOut("\n Triggered full leveling.\n");
+        
+        DDR_SDTIM1; //Read MMR to ensure full leveling is complete
+        
+        DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
+    }
+    else
+    {
+        DDR3PLLCTL1 |= 0x00000040;    //Set ENSAT = 1
+        DDR3PLLCTL1 |= 0x00002000;    //Set RESET bit before programming DDR3PLLCTL0
+        DDR3PLLCTL0 = 0x02000140;
+        
+        for(i=0;i<1000;i++); //Wait atleast 5us
+        DDR3PLLCTL1 &= 0xFFFFDFFF;    //Clear RESET bit
+        
+        DDR_SDRFC    = 0x800030D4;    // inhibit configuration
+        
+        DDR_SDTIM1   = 0x0AAAE4E3;
+        DDR_SDTIM2   = 0x20437FDA;
+        DDR_SDTIM3   = 0x559F83FF;
+        
+        DDR_DDRPHYC  = 0x0010010F;
+        
+        DDR_SDRFC    = 0x000030D4;    // enable configuration
+        
+        DDR_SDCFG    = 0x63222AB2;    // DRAM Mode Register writes occur here - 31.25us long refresh periods
+        
+        DDR3_CONFIG_REG_0 |= 0xF;         // set dll_lock_diff to 15
+        DDR3_CONFIG_REG_0 &= 0xFF801FFF;  // clear ctrl_slave_ratio field
+        DDR3_CONFIG_REG_0 |= 0x00200000;  // set ctrl_slave_ratio field to 256 since INV_CLKOUT = 1
+        
+        DDR3_CONFIG_REG_12 |= 0x08000000; // Set INV_CLKOUT = 1
+        
+        DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO | (WR_DQS_SLAVE_RATIO << 10) | (WR_DATA_SLAVE_RATIO << 20);
+        DDR3_CONFIG_REG_24 = FIFO_WE_SLAVE_RATIO;
+        
+        
+        DDR_SDRFC    = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
+    }
 
     return (0);
 
 } /* hwEmif4p0Enable */
 
-    
+
index 33419e3ab68f4f717aeea2e3751f49e011826620..fba6a7d8ecfa243fab5d688f1e1ff66280640e4b 100755 (executable)
@@ -782,7 +782,7 @@ hotmenu setConfig_c6670_main()
 {
        ibl.iblMagic = ibl_MAGIC_VALUE;
 
-       /* Main PLL: 100 MHz reference, 1GHz output */
+       /* Main PLL: 122.88 MHz reference, 983 MHz output */
        ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;
        ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
        ibl.pllConfig[ibl_MAIN_PLL].mult          = 16;
@@ -790,18 +790,18 @@ hotmenu setConfig_c6670_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
 
-    /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
-       ibl.pllConfig[ibl_NET_PLL].doEnable       = 0;
+    /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
+       ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
        ibl.pllConfig[ibl_NET_PLL].prediv         = 1;
-       ibl.pllConfig[ibl_NET_PLL].mult                   = 21;
+       ibl.pllConfig[ibl_NET_PLL].mult           = 17;
        ibl.pllConfig[ibl_NET_PLL].postdiv        = 2;
-       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1050;
+       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1044;
 
 
        ibl.ddrConfig.configDdr = 1;
@@ -845,7 +845,7 @@ hotmenu setConfig_c6670_main()
        ibl.sgmiiConfig[1].control               = 1;
        ibl.sgmiiConfig[1].txConfig      = 0x108a1;
        ibl.sgmiiConfig[1].rxConfig      = 0x700621;
-       ibl.sgmiiConfig[1].auxConfig     = 0x41;
+       ibl.sgmiiConfig[1].auxConfig     = 0x51;
 
        ibl.mdioConfig.nMdioOps = 0;
 
@@ -920,4 +920,10 @@ hotmenu setConfig_c6670_main()
     ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
 
        ibl.chkSum = 0;
-}
\ No newline at end of file
+}
+
+hotmenu setConfig_c6670_emac()
+{
+    ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY+1;
+    ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+}