First working version (Ethernet) on EVM with I2C boot
authorMike Line <m-line1@ti.com>
Thu, 13 Jan 2011 16:01:13 +0000 (11:01 -0500)
committerMike Line <m-line1@ti.com>
Thu, 13 Jan 2011 16:01:13 +0000 (11:01 -0500)
src/device/c661x/c661x.c
src/device/c661x/c661xinit.c
src/make/Makefile
src/make/ibl_c661x/i2crom.map.pre
src/make/makestg2
src/util/i2cConfig/i2cConfig.gel

index 199e9545e0e017b82ac7a2e89d57ee0987431516..a04a33172c4443f4fb2d981788b1360b27180595 100644 (file)
@@ -462,6 +462,11 @@ Int32 targetMacSend (void *vptr_device, Uint8* buffer, int num_bytes)
     int             i;
 
 
+    /* Must always setup the descriptor to have the minimum packet length */
+    if (num_bytes < 64)
+        num_bytes = 64;
+
+
     for (i = 0, hd = NULL; hd == NULL; i++, chipDelay32 (1000)) 
         hd = hwQmQueuePop (DEVICE_QM_TX_Q);
     
index e2e77048ce16df0c8eccbbf2c05b5befe6f40be1..be07171b26362c50a007fe94a9ed1456d036fc4a 100644 (file)
@@ -106,18 +106,20 @@ int32 deviceReadBootDevice (void)
     else
         params = (BOOT_PARAMS_COMMON_T *)ROM_BOOT_PARAMS_ADDR_C6616;
 
-
     switch (params->boot_mode)  {
 
 #ifndef EXCLUDE_I2C
         case BOOT_MODE_I2C:   w = BOOT_DEVICE_I2C;
+                              break;
 #endif
 
 #ifndef EXCLUDE_NOR_SPI
         case BOOT_MODE_SPI:   w = BOOT_DEVICE_SPI_NOR;
+                              break;
 #endif
 
         default:              w = BOOT_DEVICE_INVALID;
+                              break;
     
     }
 
index 01483672a86cc41ad6260d41b720f513f772dcdb..131aa387c3378898223a422d7ca294fb6b984302 100644 (file)
@@ -343,16 +343,19 @@ clean:
        make -f makestg2 cleant  ARCH=c64x TARGET=c6474
        make -f makestg2 cleant  ARCH=c64x TARGET=c6455
        make -f makestg2 cleant  ARCH=c64x TARGET=c6457
+       make -f makestg2 cleant  ARCH=c64x TARGET=c661x
        make -C ../util/bconvert       clean
        make -C ../util/btoccs         clean
        make -C ../util/i2cConfig      clean    ARCH=c64x TARGET=c6455
        make -C ../util/i2cConfig      clean    ARCH=c64x TARGET=c6472
        make -C ../util/i2cConfig      clean    ARCH=c64x TARGET=c6474
        make -C ../util/i2cConfig      clean    ARCH=c64x TARGET=c6457
+       make -C ../util/i2cConfig      clean    ARCH=c64x TARGET=c661x
        make -C ../util/nandwriter     clean    ARCH=c64x TARGET=c6455
        make -C ../util/nandwriter     clean    ARCH=c64x TARGET=c6472
        make -C ../util/nandwriter     clean    ARCH=c64x TARGET=c6474
        make -C ../util/nandwriter     clean    ARCH=c64x TARGET=c6457
+       make -C ../util/nandwriter     clean    ARCH=c64x TARGET=c661x
        make -C ../util/romparse       clean
        make -C ../test/test1              clean
        make -C ../test/test2              clean
index be6f8e08088888fe28440472a37e5fbc79eb4d90..72e8cbcaa095fc07486da5db1cdcdc26432c7df9 100644 (file)
@@ -13,7 +13,7 @@
 section 
 {
   param_index    = 0
-  boot_mode      = 257
+  boot_mode      = 40
   sw_pll_prediv         = 1
   sw_pll_mult    = 16
   sw_pll_postdiv = 2
index 0a045cc16a23dce5a5abef6b3a1bc17a70ceb6bb..8ebea6614d2906a531ca132898e96f01099ce752 100644 (file)
@@ -207,6 +207,7 @@ cleant:
        rm -rf ibl_$(TARGET)/i2crom_0x51.dat
        rm -rf ibl_$(TARGET)/i2crom.map.pp
        rm -rf ibl_$(TARGET)/ibl_init_objs.inc
+       rm -rf ibl_$(TARGET)/ibl_init_objs.pp
        rm -rf ibl_$(TARGET)/ibl_init_symbols.inc
        rm -rf ibl_$(TARGET)/ibl_objs.inc
        rm -rf ibl_$(TARGET)/ibl_objs.pp
index 7b21f81dd3058a3570d8925aa0888d9603bad630..6ee17d45c01ef048c84c6478881e2902a5ef5073 100755 (executable)
@@ -7,11 +7,19 @@
 #define ibl_LOWEST_PRIORITY     10\r
 #define ibl_DEVICE_NOBOOT       20\r
 \r
+#define ibl_PORT_SWITCH_ALL     -2\r
+\r
 #define SETIP(array,i0,i1,i2,i3)      array[0]=(i0);  \\r
                                       array[1]=(i1);  \\r
                                       array[2]=(i2);  \\r
                                       array[3]=(i3)\r
 \r
+#define  ibl_BOOT_MODE_TFTP     10\r
+#define  ibl_BOOT_MODE_NAND     11\r
+#define  ibl_BOOT_MODE_NOR      12\r
+#define  ibl_BOOT_MODE_NONE     13\r
+\r
+\r
 #define ibl_BOOT_FORMAT_AUTO    0\r
 #define ibl_BOOT_FORMAT_NAME    1\r
 #define ibl_BOOT_FORMAT_BIS     2\r
 #define ibl_DDR_PLL     1\r
 #define ibl_NET_PLL     2\r
 \r
+#define ibl_EMIF4_ENABLE_sdRamConfig                  (1 <<  0)\r
+#define  ibl_EMIF4_ENABLE_sdRamConfig2                (1 <<  1)\r
+#define  ibl_EMIF4_ENABLE_sdRamRefreshCtl             (1 <<  2)\r
+#define  ibl_EMIF4_ENABLE_sdRamTiming1                (1 <<  3)\r
+#define  ibl_EMIF4_ENABLE_sdRamTiming2                (1 <<  4)\r
+#define  ibl_EMIF4_ENABLE_sdRamTiming3                (1 <<  5)\r
+#define  ibl_EMIF4_ENABLE_lpDdrNvmTiming              (1 <<  6)\r
+#define  ibl_EMIF4_ENABLE_powerManageCtl              (1 <<  7)\r
+#define  ibl_EMIF4_ENABLE_iODFTTestLogic              (1 <<  8)\r
+#define  ibl_EMIF4_ENABLE_performCountCfg             (1 <<  9)\r
+#define  ibl_EMIF4_ENABLE_performCountMstRegSel       (1 << 10)\r
+#define  ibl_EMIF4_ENABLE_readIdleCtl                 (1 << 11)\r
+#define  ibl_EMIF4_ENABLE_sysVbusmIntEnSet            (1 << 12)\r
+#define  ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg        (1 << 13)\r
+#define  ibl_EMIF4_ENABLE_tempAlterCfg                (1 << 14)\r
+#define  ibl_EMIF4_ENABLE_ddrPhyCtl1                  (1 << 15)\r
+#define  ibl_EMIF4_ENABLE_ddrPhyCtl2                  (1 << 16)\r
+#define  ibl_EMIF4_ENABLE_priClassSvceMap             (1 << 17)\r
+#define  ibl_EMIF4_ENABLE_mstId2ClsSvce1Map           (1 << 18)\r
+#define  ibl_EMIF4_ENABLE_mstId2ClsSvce2Map           (1 << 11)\r
+#define  ibl_EMIF4_ENABLE_eccCtl                      (1 << 19)\r
+#define  ibl_EMIF4_ENABLE_eccRange1                   (1 << 20)\r
+#define  ibl_EMIF4_ENABLE_eccRange2                   (1 << 21)\r
+#define  ibl_EMIF4_ENABLE_rdWrtExcThresh              (1 << 22)\r
+#define  ibl_BOOT_EMIF4_ENABLE_ALL                    0x007fffff\r
+    \r
+/* @} */  \r
 \r
 menuitem "EVM c6472 IBL";\r
 \r
@@ -609,3 +644,141 @@ hotmenu setConfig_c6455()
 }\r
 \r
 \r
+menuitem "EVM c6608 IBL";\r
+\r
+hotmenu setConfig_c6608()\r
+{\r
+       ibl.iblMagic = ibl_MAGIC_VALUE;\r
+\r
+       /* Main PLL: 100 MHz reference, 1GHz output */\r
+       ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;\r
+       ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
+       ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
+       ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;\r
+       ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
+\r
+       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */\r
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; \r
+       ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;\r
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;\r
+       ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;\r
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;\r
+\r
+    /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */\r
+       ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;\r
+       ibl.pllConfig[ibl_NET_PLL].prediv         = 1;\r
+       ibl.pllConfig[ibl_NET_PLL].mult                   = 21;\r
+       ibl.pllConfig[ibl_NET_PLL].postdiv        = 2;\r
+       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1050;\r
+\r
+\r
+       ibl.ddrConfig.configDdr = 1;\r
+       ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;\r
+\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                         = 0x63C452B2;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2                        = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl                     = 0x000030D4;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1                        = 0x0AAAE51B;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2                        = 0x2A2F7FDA;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3                        = 0x057F82B8;\r
+       ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming                      = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.powerManageCtl                      = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic                      = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.performCountCfg                     = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel       = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                         = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet            = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg        = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg                        = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                          = 0x0010010d;\r
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                          = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap                     = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map           = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map           = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.eccCtl                                      = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.eccRange1                           = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.eccRange2                           = 0;\r
+       ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh                      = 0;\r
+\r
+\r
+       ibl.sgmiiConfig[0].configure     = 1;\r
+       ibl.sgmiiConfig[0].adviseAbility = 1;\r
+       ibl.sgmiiConfig[0].control               = 1;\r
+       ibl.sgmiiConfig[0].txConfig      = 0x108a1;\r
+       ibl.sgmiiConfig[0].rxConfig      = 0x700621;\r
+       ibl.sgmiiConfig[0].auxConfig     = 0x41;\r
+\r
+       ibl.sgmiiConfig[1].configure     = 1;\r
+       ibl.sgmiiConfig[1].adviseAbility = 1;\r
+       ibl.sgmiiConfig[1].control               = 1;\r
+       ibl.sgmiiConfig[1].txConfig      = 0x108a1;\r
+       ibl.sgmiiConfig[1].rxConfig      = 0x700621;\r
+       ibl.sgmiiConfig[1].auxConfig     = 0x41;\r
+\r
+       ibl.mdioConfig.nMdioOps = 0;\r
+\r
+       ibl.spiConfig.addrWidth  = 0;\r
+       ibl.spiConfig.nPins      = 0;\r
+       ibl.spiConfig.mode       = 0;\r
+       ibl.spiConfig.csel       = 0;\r
+       ibl.spiConfig.c2tdelay   = 0;\r
+       ibl.spiConfig.busFreqMHz = 0;\r
+\r
+       ibl.emifConfig[0].csSpace    = 0;\r
+       ibl.emifConfig[0].busWidth   = 0;\r
+       ibl.emifConfig[0].waitEnable = 0;\r
+\r
+       ibl.emifConfig[1].csSpace    = 0;\r
+       ibl.emifConfig[1].busWidth   = 0;\r
+       ibl.emifConfig[1].waitEnable = 0;\r
+\r
+       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;\r
+       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;\r
+       ibl.bootModes[0].port     = ibl_PORT_SWITCH_ALL;\r
+\r
+       ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;\r
+       ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;\r
+       ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;\r
+       ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+\r
+    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    158,218,32,118);\r
+    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp,  158,218,32,252);\r
+    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,32,2);\r
+    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask,   255,255,255,0);\r
+\r
+    /* Use the e-fuse value */\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;\r
+\r
+\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0]  = 't';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1]  = 'e';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2]  = 's';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3]  = 't';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4]  = '.';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5]  = 'b';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6]  = 'l';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7]  = 'o';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8]  = 'b';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9]  = '\0';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = '\0';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = '\0';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';\r
+    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';\r
+\r
+    ibl.bootModes[0].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */\r
+    ibl.bootModes[0].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
+    ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */\r
+\r
+\r
+       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;\r
+\r
+       ibl.chkSum = 0;\r
+\r
+}\r