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raw | patch | inline | side by side (from parent 1: 2ac8c51)
raw | patch | inline | side by side (from parent 1: 2ac8c51)
| author | Sandeep Paulraj <s-paulraj@ti.com> | |
| Fri, 1 Jul 2011 15:57:39 +0000 (11:57 -0400) | ||
| committer | Sandeep Paulraj <s-paulraj@ti.com> | |
| Fri, 1 Jul 2011 15:57:39 +0000 (11:57 -0400) |
This commit adds infrastructure to build the 6474
low cost EVM as a separate target
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
low cost EVM as a separate target
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
17 files changed:
diff --git a/src/cfg/c6474l/iblcfg.h b/src/cfg/c6474l/iblcfg.h
--- /dev/null
+++ b/src/cfg/c6474l/iblcfg.h
@@ -0,0 +1,124 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/**************************************************************************
+ * FILE PURPOSE: Provide build time configurations for the IBL
+ **************************************************************************
+ * FILE NAME: iblcfg.h
+ *
+ * DESCRIPTION: Build time configuration
+ *
+ * @file iblcfg.h
+ *
+ * @brief
+ * Build time configurations for the c6474l ibl are defined
+ *
+ ***************************************************************************/
+#ifndef IBLCFG_H
+#define IBLCFG_H
+
+/**
+ * @brief The maximum number of UDP sockets in the system
+ */
+#define MAX_UDP_SOCKET 3
+
+
+/**
+ * @brief The maximum number of timers in the system
+ */
+#define MAX_TIMER_BLOCKS 5
+
+
+/**
+ * @brief The size in bytes of the internal stream buffer
+ */
+#define MAX_SIZE_STREAM_BUFFER 1024
+
+
+/**
+ * @brief The maximum number of functions supported for BIS mode
+ */
+#define MAX_BIS_FUNCTION_SUPPORT 3
+
+
+/**
+ * @brief No I/O sections accepted in boot table format
+ */
+#define BOOTCONFIG_NO_BTBL_IO
+
+/**
+ * @brief The I2C bus address and data address of the ibl table.
+ */
+#define IBL_CFG_I2C_DEV_FREQ_MHZ 1000
+#define IBL_CFG_I2C_CLK_FREQ_KHZ 100
+#define IBL_CFG_I2C_OWN_ADDR 10
+#define IBL_CFG_I2C_ADDR_DELAY 0x100 /* Delay between sending the address and reading data */
+
+/**
+ * @brief The default location for the i2c map information can be overridden during make
+ */
+#ifndef IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR
+ #define IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR 0x50
+#endif
+
+#ifndef IBL_CFG_I2C_MAP_TABLE_DATA_ADDR
+ #define IBL_CFG_I2C_MAP_TABLE_DATA_ADDR 0x100
+#endif
+
+/**
+ * @brief
+ * GPIO pin mapping
+ */
+#define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
+#define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
+#define NAND_NWE_GPIO_PIN GPIO_10
+#define NAND_BSY_GPIO_PIN GPIO_11 /* NAND Ready/Busy pin */
+#define NAND_NRE_GPIO_PIN GPIO_12
+#define NAND_NCE_GPIO_PIN GPIO_13
+#define NAND_MODE_GPIO GPIO_14
+
+/**
+ * @brief
+ * The standard NAND delay must be big enough to handle the highest possible
+ * operating frequency of the device */
+#define TARGET_NAND_STD_DELAY 25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY (10000)
+
+
+#endif
+
+
diff --git a/src/device/c6474l/c6474l.c b/src/device/c6474l/c6474l.c
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/************************************************************************************
+ * FILE PURPOSE: C6474 Device Specific functions
+ ************************************************************************************
+ * FILE NAME: c6474.c
+ *
+ * DESCRIPTION: Implements the device specific functions for the IBL
+ *
+ * @file c6474.c
+ *
+ * @brief
+ * This file implements the device specific functions for the IBL
+ *
+ ************************************************************************************/
+#include "ibl.h"
+#include "device.h"
+#include "pllapi.h"
+#include "emif31api.h"
+#include "pscapi.h"
+#include "gpio.h"
+#include "nandhwapi.h"
+#include <string.h>
+
+extern cregister unsigned int DNUM;
+
+
+/**
+ * @brief Determine if an address is local
+ *
+ * @details
+ * Examines an input address to determine if it is a local address
+ */
+bool address_is_local (Uint32 addr)
+{
+ /* L2 */
+ if ((addr >= 0x00800000) && (addr < 0x00898000))
+ return (TRUE);
+
+ /* L1P */
+ if ((addr >= 0x00e00000) && (addr < 0x00e08000))
+ return (TRUE);
+
+ /* L2D */
+ if ((addr >= 0x00f00000) && (addr < 0x00f08000))
+ return (TRUE);
+
+ return (FALSE);
+
+}
+
+
+/**
+ * @brief Convert a local l1d, l1p or l2 address to a global address
+ *
+ * @details
+ * The global address is formed. If the address is not local then
+ * the input address is returned
+ */
+Uint32 deviceLocalAddrToGlobal (Uint32 addr)
+{
+
+ if (address_is_local (addr))
+ addr = (1 << 28) | (DNUM << 24) | addr;
+
+ return (addr);
+
+}
+
+
+/**
+ * @brief
+ * Enable the DDR
+ *
+ * @details
+ * The DDR controller on the c6474 is an emif 3.1. The controller is
+ * initialized directly with the supplied values
+ */
+void deviceDdrConfig (void)
+{
+ if (ibl.ddrConfig.configDdr != 0)
+ hwEmif3p1Enable (&ibl.ddrConfig.uEmif.emif3p1);
+
+}
+
+
+/**
+ * @brief Power up a peripheral
+ *
+ * @details
+ * Boot peripherals are powered up
+ */
+int32 devicePowerPeriph (int32 modNum)
+{
+ /* If the input value is < 0 there is nothing to power up */
+ if (modNum < 0)
+ return (0);
+
+
+ if (modNum >= TARGET_PWR_MAX_MOD)
+ return (-1);
+
+ return ((int32)pscEnableModule(modNum));
+
+}
+
+
+/**
+ * @brief Enable the pass through version of the nand controller
+ *
+ * @details On the evm the nand controller is enabled by setting
+ * gpio 14 high
+ */
+#ifndef EXCLUDE_NAND_GPIO
+int32 deviceConfigureForNand(void)
+{
+ hwGpioSetDirection(NAND_MODE_GPIO, GPIO_OUT);
+ hwGpioSetOutput(NAND_MODE_GPIO);
+ return (0);
+
+}
+#endif
+
+
+/**
+ * @brief
+ * The e-fuse mac address is loaded
+ */
+void deviceLoadDefaultEthAddress (uint8 *maddr)
+{
+ uint32 macA, macB;
+
+ /* Read the e-fuse mac address */
+ macA = *((uint32 *)0x2880834);
+ macB = *((uint32 *)0x2880838);
+
+ maddr[0] = (macB >> 8) & 0xff;
+ maddr[1] = (macB >> 0) & 0xff;
+ maddr[2] = (macA >> 24) & 0xff;
+ maddr[3] = (macA >> 16) & 0xff;
+ maddr[4] = (macA >> 8) & 0xff;
+ maddr[5] = (macA >> 0) & 0xff;
+}
+
+/**
+ * @brief Return the NAND interface call table. Only GPIO is supported on c6474
+ */
+
+#ifndef EXCLUDE_NAND_GPIO
+nandCtbl_t nandCtbl = {
+
+ nandHwGpioDriverInit,
+ nandHwGpioDriverReadBytes,
+ nandHwGpioDriverReadPage,
+ nandHwGpioDriverClose
+
+};
+
+nandCtbl_t *deviceGetNandCtbl (int32 interface)
+{
+ return (&nandCtbl);
+}
+#endif
+
+
+
+
+
diff --git a/src/device/c6474l/c6474linit.c b/src/device/c6474l/c6474linit.c
--- /dev/null
@@ -0,0 +1,56 @@
+/**
+ * @file c6474init.c
+ *
+ * @brief
+ * c6474 functions used during the initial stage of the ibl load
+ */
+#include "ibl.h"
+#include "device.h"
+#include "pllapi.h"
+
+#pragma DATA_SECTION(idle_c1, ".idle_c1")
+
+const unsigned int idle_c1 = 0x0001e000; /* This is an idle instruction */
+
+#pragma DATA_SECTION(idle_c2, ".idle_c2")
+
+const unsigned int idle_c2 = 0x0001e000; /* This is an idle instruction */
+
+
+
+/**
+ * @brief Configure the PLLs
+ *
+ * @details
+ * Only the main PLL can be configured here. The DDR pll is enabled by default,
+ * and the network PLL is enabled through serdes configuration.
+ * the multiplier and dividers.
+ */
+void devicePllConfig (void)
+{
+ if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv,
+ ibl.pllConfig[ibl_MAIN_PLL].mult,
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+}
+
+
+/**
+ * @brief
+ * Return the endian status of the device
+ *
+ * @details
+ * Returns true if the device is executing in little endian mode
+ */
+extern cregister volatile unsigned int CSR;
+
+bool deviceIsLittleEndian (void)
+{
+ if ((CSR & (1 << 8)) == 0)
+ return (FALSE);
+
+ return (TRUE);
+
+}
diff --git a/src/device/c6474l/target.h b/src/device/c6474l/target.h
--- /dev/null
@@ -0,0 +1,227 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/**************************************************************************
+ * FILE PURPOSE: Target specific definitions
+ **************************************************************************
+ * FILE NAME: target.h
+ *
+ * DESCRIPTION: This file defines target specific values used by low level
+ * drivers.
+ *
+ * @file target.h
+ *
+ * @brief
+ * Low level target specific values are defined
+ *
+ ***************************************************************************/
+
+
+/**
+ * @brief
+ * Device EMAC definitions
+ */
+#define TARGET_DEVICE_CPMAC
+
+#define TARGET_EMAC_N_PORTS 1
+
+#define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }
+#define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }
+
+#define TARGET_SGMII_BASE_ADDRESSES { 0x02c40000u }
+
+/* SGMII offsets (at least the serdes configs, vary between devices, so
+ * they are defined here. */
+#define TARGET_SGMII_IDVER 0x000
+#define TARGET_SGMII_SOFT_RESET 0x004
+#define TARGET_SGMII_CONTROL 0x010
+#define TARGET_SGMII_STATUS 0x014
+#define TARGET_SGMII_MR_ADV_ABILITY 0x018
+#define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020
+#define TARGET_SGMII_TX_CFG 0x030
+#define TARGET_SGMII_RX_CFG 0x034
+#define TARGET_SGMII_AUX_CFG 0x038
+
+/* Leave mdio disabled */
+#define dev_mdio_open() 1
+
+/* No chip level reset required for ethernet, the function call is made a void statment */
+#define deviceSetEthResetState(x,y)
+
+/* The mac control register values */
+#define TARGET_MAC_CONTROL ( 1 << 18) /* EXT_EN */ \
+ | ( 0 << 9 ) /* Round robin */ \
+ | ( 1 << 7 ) /* GIG */ \
+ | ( 0 << 6 ) /* TX pacing disabled */ \
+ | ( 1 << 5 ) /* GMII RX & TX */ \
+ | ( 0 << 4 ) /* TX flow disabled */ \
+ | ( 0 << 3 ) /* RX flow disabled */ \
+ | ( 0 << 1 ) /* Loopback enabled */ \
+ | ( 1 << 0 ) /* full duplex */
+
+
+/**
+ * @brief
+ * Device Timer definitions
+ */
+#define TIMER0_BASE 0x02910000u
+
+#define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
+
+
+/**
+ * @def MAIN_PLL
+ */
+#define MAIN_PLL 0 /**< The index to the main PLL */
+
+
+/**
+ * @brief
+ * Device PLL definitions
+ */
+#define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : 0)
+
+
+/**
+ * @brief
+ * Device PSC definitions
+ */
+#define DEVICE_PSC_BASE 0x02ac0000u
+
+/**
+ * @brief
+ * The ethernet is in the always on domain */
+#define TARGET_PWR_ETH(x) -1
+
+/**
+ * @brief
+ * The nand is done through gpio, which is always powered up.
+ * A value < 0 tells the low level psc driver to simply return success
+ */
+#define TARGET_PWR_NAND -1
+
+/**
+ * @brief
+ * The PSC number for GPIO. GPIO is in the always on domain
+ */
+#define TARGET_PWR_GPIO -1
+
+
+/**
+ * @brief
+ * Flag to indicate timer 0 power up requested. The time is always on in the
+ * 6474l
+ */
+#define TARGET_PWR_TIMER_0 -1
+
+
+/**
+ * @brief
+ * Device DDR controller definitions
+ */
+#define DEVICE_DDR_BASE 0x70000000
+#define targetEmifType() ibl_EMIF_TYPE_31
+
+/**
+ * @brief
+ * The highest module number
+ */
+#define TARGET_PWR_MAX_MOD 5
+
+
+/**
+ * @brief
+ * The base address of MDIO
+ */
+#define TARGET_MDIO_BASE 0x2c81800
+
+/**
+ * @brief
+ * GPIO address
+ */
+#define GPIO_GPIOPID_REG 0x02B00000
+#define GPIO_GPIOEMU_REG 0x02B00004
+#define GPIO_BINTEN_REG 0x02B00008
+#define GPIO_DIR_REG 0x02B00010
+#define GPIO_OUT_DATA_REG 0x02B00014
+#define GPIO_SET_DATA_REG 0x02B00018
+#define GPIO_CLEAR_DATA_REG 0x02B0001C
+#define GPIO_IN_DATA_REG 0x02B00020
+#define GPIO_SET_RIS_TRIG_REG 0x02B00024
+#define GPIO_CLR_RIS_TRIG_REG 0x02B00028
+#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
+#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
+
+#define ECC_BLOCK_SIZE 256
+
+/* NAND address pack macro */
+#define PACK_ADDR(col, page, block) \
+ ((col & 0x00000fff) | ((page & 0x0000003f)<<16) | ((block & 0x000003ff) << 22 ))
+
+/**
+ * @brief
+ * The base address of the I2C peripheral, and the module divisor of the cpu clock
+ */
+#define DEVICE_I2C_BASE 0x02b04000
+#define DEVICE_I2C_MODULE_DIVISOR 6
+
+
+/**
+ * @brief
+ * Register access macros
+ */
+#define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
+#define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
+
+#define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
+#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
+#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
+
+
+/**
+ * @brief
+ * The c6474l supports only booting the ibl from i2c
+ */
+#define deviceReadBootDevice() BOOT_DEVICE_I2C
+
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+
+
diff --git a/src/device/c6474l/tiboot_c6474.h b/src/device/c6474l/tiboot_c6474.h
--- /dev/null
@@ -0,0 +1,570 @@
+#ifndef __TIBOOT_H__
+#define __TIBOOT_H__
+/******************************************************************************
+ * FILE PURPOSE: Define Structures, MACROs and etc for TI Shared ROM Boot
+ ******************************************************************************
+ * FILE NAME: tiboot.h
+ *
+ * DESCRIPTION: Define structures, macros and etc for the TI Shared ROM boot
+ * process.
+ *
+ * TABS: NONE
+ *
+ * $Id: $
+ *
+ * REVISION HISTORY:
+ *
+ * $Log: $
+ *
+ * (C) Copyright 2004 TELOGY Networks, Inc.
+ ******************************************************************************/
+#include "types.h"
+
+/*******************************************************************************
+ * Utility Macro definitions
+ ******************************************************************************/
+#define HEX_DIGIT(digit) ((digit) + '0')
+#define BOOT_BIT_TO_MASK(bit) (1 << (bit))
+
+/*******************************************************************************
+ * Data Definition: Error Handling relatBOOT_ENTRY_POINT_ADDRed definition:
+ *******************************************************************************
+ * Description: Define Handling related macros, constants
+ *
+ ******************************************************************************/
+/* Define Module IDs */
+#define BOOT_MODULE_ID_MAIN 0
+#define BOOT_MODULE_ID_BTBL 1
+#define BOOT_MODULE_ID_BETH 2
+#define BOOT_MODULE_ID_I2C 3
+#define BOOT_MODULE_ID_CHIP 4
+#define BOOT_MODULE_ID_HW 5
+
+/* Boot error codes */
+enum {
+ BOOT_NOERR = 0,
+ BOOT_ERROR = 1, /* General error */
+ BOOT_INVALID_BOOT_MODE = 2,
+ BOOT_INVALID_I2C_DEV_ADDR = 3,
+ BOOT_INVALID_CHECKSUM = 4, /* Invalid checksum of the boot parameters */
+ BOOT_INVALID_PARAMS_SIZE = 5, /* the size of boot parameters is too big */
+ BOOT_RX_ETH_QUEUE_FULL = 6, /* ethmain.c, hw_rxPacket */
+ BOOT_CACHE_INIT_FAIL = 7, /* rmain.c, cache init failed */
+ BOOT_CACHE_DISABLE_FAIL = 8, /* rmain.c, cache disable failed */
+ BOOT_INVALID_CPPI_SIZE = 9, /* ethmain.c, invalid compile sizes */
+ BOOT_INVALID_CORE_ID = 10, /* Invalid core ID in cold boot */
+ BOOT_INVALID_MAC_ADDR = 11, /* Invalid MAC address (all 0's) */
+ BOOT_ETH_TX_SCRATCH = 12, /* tx scratch size invalid */
+ BOOT_ETH_TX_PACKET = 13, /* tx packet formation failure */
+ BOOT_ETH_MAC_INIT = 14, /* ethmain.c - mac init failed */
+ BOOT_PERIPH_POWER = 15, /* peripheral failed to powerup */
+ BOOT_MAIN_FAIL = 16, /* Failed in initial boot setup (wrong core) */
+ BOOT_SK_REGISTERSCWP = 17, /* Failed at SK_registerSCWP */
+ BOOT_SK_ALLOCSC = 18, /* Failed at SK_allocSC */
+ BOOT_CPSGMII_CONFIGINDEX = 19, /* Failed at wrong CPSGMII config index */
+ BOOT_SRIO_CONFIGINDEX = 20 /* Failed at wrong SRIO config index */
+};
+
+/* Error tracking prototypes (functions in rmain.c)*/
+void bootException (UINT16 errorCode);
+void bootError (UINT16 errorCode);
+
+/* Error code = (module ID * 100) + module specific error */
+#define BOOT_ERROR_CODE(id, code) ((UINT16)((id<<8) + code))
+#define BOOT_EXCEPTION(error_code) bootException(error_code)
+#define BOOT_ERROR(error_code) bootError(error_code)
+
+/*******************************************************************************
+ * Begin Boot Parameter definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Boot Parameter Common
+ ******************************************************************************/
+typedef struct boot_params_common_s{
+ UINT16 length; /* size of the entire boot parameters in bytes */
+ UINT16 checksum; /* non-zero: 1's complement checksum of the boot
+ * parameters
+ * zero: checksum is not applicable
+ */
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPll; /* CPU PLL multiplier */
+
+
+} BOOT_PARAMS_COMMON_T;
+
+typedef struct boot_params_ethernet_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPll; /* CPU PLL multiplier */
+
+ /* Etherent specific portion of the Boot Parameters */
+ UINT16 options;
+ /*
+ * Ethernet Specific Options
+ *
+ * Bits 2:0 interface
+ * 000 - MII
+ * 001 - RMII
+ * 010 - GMII
+ * 011 - RGMII
+ * 100 - SMII
+ * 101 - S3MII
+ *
+ * Bit 3: HD:
+ * 0 - Full Duplex
+ * 1 - Half Duplex
+ * Bit 4: SKIP TX
+ * 0 - Send the Ethernet Ready Frame
+ * 1 - Skip sending the Ethernet Ready Frame
+ * Bit 5: SKIP INIT
+ * 0 - Initialize the Ethernet MAC peripheral
+ * 1 - Skip initializing the Ethernet MAC peripheral
+ * Bit 6: FC
+ * 0 - Disable Flow Control
+ * 1 - Enable Flow Control
+ *
+ * Other bits: Reserved
+ */
+ #define BOOT_PARAMS_ETH_OPTIONS_MII 0x0000
+ #define BOOT_PARAMS_ETH_OPTIONS_RMII 0x0001
+ #define BOOT_PARAMS_ETH_OPTIONS_GMII 0x0002
+ #define BOOT_PARAMS_ETH_OPTIONS_RGMII 0x0003
+ #define BOOT_PARAMS_ETH_OPTIONS_SMII 0x0004
+ #define BOOT_PARAMS_ETH_OPTIONS_S3MII 0x0005
+
+ /* Faraday only supports SGMII */
+ #define BOOT_PARAMS_ETH_OPTIONS_SGMII 0x0006
+
+ #define BOOT_PARAMS_ETH_OPTIONS_HD 0x0008
+ #define BOOT_PARAMS_ETH_OPTIONS_SKIP_TX 0x0010
+ #define BOOT_PARAMS_ETH_OPTIONS_SKIP_INIT 0x0020
+ #define BOOT_PARAMS_ETH_OPTIONS_FC 0x0040
+
+ /*
+ * he device MAC address to be used for Boot:
+ * All zero mac address indicates that the device E-fuse address should
+ * be used.
+ */
+ UINT16 mac_addr_h;
+ UINT16 mac_addr_m;
+ UINT16 mac_addr_l;
+
+ /*
+ * The multicast or broadcast MAC address which should be accepted as
+ * a destination MAC address for boot table frames
+ */
+ UINT16 mmac_addr_h;
+ UINT16 mmac_addr_m;
+ UINT16 mmac_addr_l;
+
+ UINT16 src_port; /* Source UDP port number to be used during boot process */
+ /* 0: allow any SRC UDP port */
+ UINT16 dest_port; /* Destination UDP port number to be used during boot process */
+
+ /* The Device ID to be included in the boot ready announcement frame */
+ UINT16 device_id_12;
+ UINT16 device_id_34;
+ #define BOOT_PARAMS_DEVICE_ID_HIGH_MASK 0xFF00
+ #define BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT 8
+ #define BOOT_PARAMS_DEVICE_ID_LOW_MASK 0x00FF
+ #define BOOT_PARAMS_DEVICE_ID_LOW_SHIFT 0
+ #define BOOT_PARAMS_GET_DEVICE_ID_13(device_id) \
+ (((device_id) & BOOT_PARAMS_DEVICE_ID_HIGH_MASK) > BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT)
+ #define BOOT_PARAMS_GET_DEVICE_ID_24(device_id) \
+ (((device_id) & BOOT_PARAMS_DEVICE_ID_LOW_MASK) > BOOT_PARAMS_DEVICE_ID_LOW_SHIFT)
+
+ /*
+ * The destination MAC address used for the boot ready announce frame
+ */
+ UINT16 hmac_addr_h;
+ UINT16 hmac_addr_m;
+ UINT16 hmac_addr_l;
+
+ /*
+ * The CPSGMII configurations for Faraday
+ */
+
+ UINT16 sgmiiConfig;
+
+ #define BOOT_PARAMS_SGMII_CONFIG_INDEX_MASK 0x0F /* bit 3 to 0 is index */
+ #define BOOT_PARAMS_SGMII_CONFIG_DIRECT_CONFIG (1<<4) /* set to use direct configurations */
+ #define BOOT_PARAMS_SGMII_CONFIG_NO_CONFIG (1<<5) /* set to bypass CPSGMII config */
+
+ UINT16 sgmiiControl;
+ #define BOOT_PARAMS_SGMII_CONTROL_MASK 0x7F
+
+ UINT16 sgmiiMr_Adv_Ability;
+ #define BOOT_PARAMS_SGMII_ABILITY_MASK 0x0000FFFF
+
+ UINT16 sgmiiTx_Cfg_h;
+ UINT16 sgmiiTx_Cfg_l;
+ UINT16 sgmiiRx_Cfg_h;
+ UINT16 sgmiiRx_Cfg_l;
+ UINT16 sgmiiAux_Cfg_h;
+ UINT16 sgmiiAux_Cfg_l;
+
+} BOOT_PARAMS_ETHERNET_T;
+
+/**************************************************************************************
+ * Utopia boot options
+ **************************************************************************************/
+typedef struct boot_params_utopia_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPll; /* CPU PLL multiplier */
+
+ /* Utopia specific portion of the Boot Parameters */
+ /* Options
+ * ---------------------------------------------------------------
+ * | 15 3 | 2 | 1 | 0 |
+ * ----------------------------------------------------------------
+ * reserved | | \-> 0 = multi phy
+ * | | 1 = single phy
+ * | \-> 0 = 8 bit utopia
+ * | 1 = 16 bit utopis
+ * \-> 0 = Init port
+ * 1 = skip port init
+ */
+ UINT16 options;
+
+ #define BOOT_PARAMS_UTOPIA_SINGLE_PHY (1<<0)
+ #define BOOT_PARAMS_UTOPIA_16BIT (1<<1)
+ #define BOOT_PARAMS_UTOPIA_SKIP_INIT (1<<2)
+
+ UINT16 cellSizeBytes; /* Cell Size */
+ UINT16 busWidthBits; /* Bus width (8 or 16) */
+ UINT16 slid; /* Slave ID */
+ UINT16 coreFreqMhz; /* CPU frequency after pll mult */
+
+
+} BOOT_PARAMS_UTOPIA_T;
+
+typedef struct boot_params_i2c_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPll; /* CPU PLL multiplier */
+
+ /* I2C specific portion of the Boot Parameters */
+ UINT16 options;
+ /*
+ * I2C Specific Options
+ * Bit 01-00: BT:
+ * 00 - Boot Parameter Mode
+ * 01 - Boot Table Mode
+ * 10 - Boot Config mode
+ * 11 - Slave receive boot config
+ * Bit 04-02: EETYPE: EEPROM type
+ * Other bits: Reserved
+ */
+ #define BOOT_PARAMS_I2C_OPTIONS_BP 0x0000
+ #define BOOT_PARAMS_I2C_OPTIONS_BT 0x0001
+ #define BOOT_PARAMS_I2C_OPTIONS_BC 0x0002
+ #define BOOT_PARAMS_I2C_OPTIONS_SLVOPT 0x0003
+
+ #define BOOT_PARAMS_I2C_OPTIONS_MASK 0x0003
+ #define BOOT_PARAMS_I2C_OPTIONS_SHIFT 0
+
+ #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK 0x001C
+ #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT 2
+
+ #define BOOT_PARAMS_I2C_IS_BOOTTBL_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BT)
+
+ #define BOOT_PARAMS_I2C_IS_BOOTCONFIG_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BC)
+
+ #define BOOT_PARAMS_I2C_IS_SLAVE_RCV_OPTIONS_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_SLVOPT)
+
+ #define BOOT_PARAMS_I2C_IS_BOOTPARAM_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BP)
+
+ #define BOOT_PARAMS_I2C_SET_BOOTTBL_MODE(options, mode) \
+ (options) = ((options) & ~BOOT_PARAMS_I2C_OPTIONS_MASK) | \
+ (((mode) & BOOT_PARAMS_I2C_OPTIONS_MASK) << \
+ BOOT_PARAMS_I2C_OPTIONS_SHIFT)
+
+
+ #define BOOT_PARAMS_I2C_GET_EETYPE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) >> BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT)
+ #define BOOT_PARAMS_I2C_SET_EETYPE(options, ee_type) \
+ (options) = (((options) & ~BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) | \
+ (((ee_type) << BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK))
+
+ /* The device address to be used for Boot */
+ UINT16 dev_addr; /* 16-bit device address (low) */
+ UINT16 dev_addr_ext; /* 16-bit extended device address (high)
+ * set to zero if not used
+ * Note: some I2C device requires 32-bit
+ * address
+ */
+ UINT16 multi_i2c_id; /* Multi device master write boot ID */
+ UINT16 my_i2c_id; /* This parts I2C address */
+
+ UINT16 core_freq_mhz; /* Core frequency, MHz */
+ UINT16 i2c_clk_freq_khz; /* Desired I2C clock frequency, kHz */
+
+ UINT16 next_dev_addr; /* Used only for the boot config mode. */
+ UINT16 next_dev_addr_ext; /* Copied into dev_addr* after config complete */
+
+ UINT16 address_delay; /* Rough number of cycles delay between address write
+ * and read to the i2c eeprom */
+
+
+} BOOT_PARAMS_I2C_T;
+
+
+typedef struct boot_params_rapidio_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPll; /* CPU PLL multiplier */
+
+ /* Options */
+ UINT16 options;
+
+ #define BOOT_PARAMS_RIO_OPTIONS_TX_ENABLE (1<<0) /* set to enable transmit */
+ #define BOOT_PARAMS_RIO_OPTIONS_BOOT_TABLE (1<<1) /* set to use boot tables */
+ #define BOOT_PARAMS_RIO_OPTIONS_NO_CONFIG (1<<2) /* set to bypass port config */
+
+ UINT16 cfg_index; /* General configuration index to use */
+ UINT16 node_id; /* The node id for this device */
+ UINT16 serdes_ref_clk; /* The serdes reference clock freq, in MHz */
+ UINT16 link_rate; /* Data link rate (mega bits per second */
+ UINT16 pf_low; /* Packet forward range, low */
+ UINT16 pf_high; /* Packet forward range, high */
+
+} BOOT_PARAMS_RIO_T;
+
+/*
+ * UNION of boot parameter structures in all modes
+ * Note: We need to make sure that the structures genertaed by the C-compiler
+ * match with the boot parameter table data format i.e. a set of 16-bit
+ * data array.
+ */
+#define BOOT_PARAMS_SIZE_IN_BYTES 128
+typedef union {
+ BOOT_PARAMS_COMMON_T common;
+ BOOT_PARAMS_ETHERNET_T eth;
+ BOOT_PARAMS_I2C_T i2c;
+ BOOT_PARAMS_UTOPIA_T utopia;
+ BOOT_PARAMS_RIO_T rio;
+ UINT16 parameter[BOOT_PARAMS_SIZE_IN_BYTES/2];
+} BOOT_PARAMS_T;
+
+
+/*******************************************************************************
+ * Definition: The time stamp and version number are placed into the stats.
+ * This will be two characters packed per 16bits . The length
+ * value must be 32 bit divisible
+ *******************************************************************************/
+#define BOOT_VERSION_LEN_UINT16 32
+typedef struct BOOT_VERSION_S {
+
+ UINT16 vstring[BOOT_VERSION_LEN_UINT16];
+
+} BOOT_VERSION_T;
+extern BOOT_VERSION_T bootVersion;
+
+
+/*******************************************************************************
+ * Definition: Runs time stats that are not initialized on cold boot entry
+ * !!!!!! boot.s assumes that the nonInit stats are at the top of the structure
+ * !!!!!! and that stage is the first element
+ *******************************************************************************/
+typedef struct BOOT_STATS_NONINIT_S {
+ UINT16 stage; /* Record the SharedROM code execution stage */
+ #define BOOT_STAGE_ASM_START_UP 1
+ #define BOOT_STAGE_INIT_CACHE 2
+ #define BOOT_STAGE_CHCHE_INITED 3
+ #define BOOT_STAGE_ENTER_WARMBOOT 4
+ #define BOOT_STAGE_INIT_CPGMAC 5
+ #define BOOT_STAGE_SEND_ERA_FRAME 6
+ #define BOOT_STAGE_ETH_MAIN_LOOP 7
+ #define BOOT_STAGE_I2C_BOOTTBL_LOOP 8
+ #define BOOT_STAGE_I2C_BOOTPARAM_LOOP 9
+ #define BOOT_STAGE_DISABLE_CACHE 10
+ #define BOOT_STAGE_CHCHE_DISABLED 11
+ #define BOOT_STAGE_EXIT 12
+ #define BOOT_STAGE_ERROR_LOOP 13
+ #define BOOT_STAGE_I2C_BOOTCONFIG_LOOP 14
+ #define BOOT_STAGE_I2C_SLV_RCV_OPTIONS_LOOP 15
+ #define BOOT_STAGE_UTOPIA_MAIN_LOOP 16
+ UINT16 coldBootEntries;
+
+} BOOT_STATS_NONINIT_T;
+
+/*******************************************************************************
+ * Definition: Run time statistics and error counts. These stats are
+ * initialized on cold boot entry.
+ ******************************************************************************/
+
+typedef struct BOOT_STATS_COMMON_S {
+ UINT32 bootStatus;
+ UINT16 nColdBootEntries;
+ UINT16 nBootReentries;
+ UINT16 nPllWarns;
+ UINT16 nResetWarns;
+} BOOT_STATS_COMMON_T;
+
+
+typedef struct BOOT_STATS_MAIN_S {
+ UINT16 errorCode; /* (module ID <<8 ) + module specific error */
+
+ /* I2C operation related statistics */
+ UINT16 numI2Cpkts; /* number of I2C boot table packets processed */
+ UINT16 numI2CchksumError;/* number of I2C checksum errors */
+ UINT16 numI2ClengthError;/* number of I2C block length errors */
+ UINT16 numI2CotherError; /* number of I2C section with invalid length and etc */
+ UINT16 numI2Cretrys; /* number of I2C retrys due to read access errors */
+ UINT16 numI2cWrites; /* number of I2C master writes to passive devices */
+ UINT16 numI2cWriteError; /* number of I2C master write errors */
+
+ UINT16 warmBootEntry; /* Count of entries into warm boot routine */
+} BOOT_STATS_MAIN_T;
+
+
+
+/*****************************************************************************
+ * Definition: I2C stats, Boot table and Ethernrt stats initialized
+ * on cold boot entry
+ *****************************************************************************/
+typedef struct I2C_STATS_tag
+{
+ UINT16 num_trans;
+ UINT16 num_trys;
+ UINT16 num_try_ok;
+ UINT16 num_try_lost_arb;
+ UINT16 num_try_idle_to;
+ UINT16 num_try_no_ack;
+ UINT16 num_try_other_err;
+ UINT32 extra_idle_waits;
+ UINT32 extra_clock_waits;
+ UINT32 tx_bytes;
+ UINT32 rx_bytes;
+ UINT32 data_re_reads;
+} I2C_STATS_T;
+
+typedef struct BTBL_STATS_tag
+{
+ UINT16 num_sections; /* number of boot table sections received */
+ UINT16 num_pdma_copies; /* number of PDMA copies performed */
+} BTBL_STATS_T;
+
+typedef struct ETH_STATS_tag
+{
+ /* MAC packets related statistics */
+ UINT16 uniMacPkts; /* Count of packets received with valid unicast mac
+ address */
+ UINT16 multiMacPkts; /* Count of packets received with valid multicast or
+ broadcast mac address */
+ UINT16 invalidMacPkts; /* Count of packets received with invalid mac
+ address */
+ UINT16 invalidLLCPkts; /* Count of 802.3 packets with wrong LLC/SNAP header */
+ UINT16 nonIpPkts; /* Count of non-IP packets received with valid
+ MAC address */
+
+ /* IP packets related statistics */
+ UINT16 nonIP4Pkts; /* Count of non-IP4 packets */
+ UINT16 ipfragments; /* Count of IP fragments received */
+ UINT16 ipTruncatedError; /* Count of truncated IP frame */
+ UINT16 nonUDPPkts; /* Count of IP packets with non-UDP paylaod */
+
+ /* UDP packets related statistics */
+ UINT16 udpSizeError; /* Count of UDP packet with invalid (odd) size */
+ UINT16 udpPortError; /* Count of UDP packets with invalid port number */
+ UINT16 udpChksumError; /* Count of UDP packets with checksum error */
+
+ /* Boot table packets related statistics */
+ UINT16 nonBtblPkts; /* Count of UDP packets with invalid boot table paylaod */
+ UINT16 outSeqPkts; /* Count of out of sequence boot table packets received
+ i.e. packets with unexpected seq_num */
+ UINT16 expSeqNum; /* Expected Sequence Number */
+ UINT16 lastSeqNum; /* Last sequence number received */
+
+ /* Driver errors */
+ UINT16 sizeZeroPackets; /* Count of packets arriving with 0 size */
+} ETH_STATS_T;
+
+typedef struct PCI_EEAI_STATS_tag
+{
+ UINT16 pciI2cReads; /* Count of block reads of i2c eeprom */
+ UINT16 pciI2cRetries; /* Count of i2c read retries */
+ UINT16 pciChkSumErr; /* Count of block check sum errors */
+ UINT16 pciEeaiFail; /* Count of aborted pci attempts */
+} PCI_EEAI_STATS_T;
+
+/* Rapid I/O stats */
+typedef struct RAPIDIO_STATS_tag
+{
+ UINT16 rapidIoFailReady; /* If set rapid I/O peripheral failed to report ready */
+ UINT16 rapidIoBtblBlocks; /* Count of number of boot table blocks received */
+ UINT16 rapidIoBtblBadBlocks; /* Count of boot table blocks rejected */
+} RAPIDIO_STATS_T;
+
+typedef struct HPI_STATS_Tag
+{
+ UINT16 hpiBtblBlocks; /* Count of boot table blocks received */
+ UINT16 hpiBtblBadBlocks; /* Count of boot table blocks rejected */
+} HPI_STATS_T;
+
+/* Utopia stats */
+typedef struct UTOPIA_STATS_tag
+{
+ UINT16 cellCount; /* Count of cells received */
+ UINT16 invalidPtr; /* Count of invalid pointers received in processing */
+ UINT16 invalidSize; /* Count of cells that were too small */
+ UINT16 cellMagicCount; /* Count of cells received with valid magic */
+ UINT16 cellMagicFailed; /* Count of cells received with invalid magic */
+ UINT16 trapNoCellMem; /* Trapped due to no cell space in memory */
+ UINT16 possibleOverrun; /* Count of possible cell buffer overruns */
+} UTOPIA_STATS_T;
+
+/*******************************************************************************
+ * Definition: The statistics
+ *
+ * !!!!!! boot.s assumes that the nonInit stats are at the top of the structure!
+ *******************************************************************************/
+typedef struct BOOT_STATS_S {
+
+ BOOT_STATS_COMMON_T common;
+ BOOT_STATS_NONINIT_T nonInit;
+ BOOT_STATS_MAIN_T main;
+ I2C_STATS_T i2c;
+ BTBL_STATS_T btbl;
+ union {
+ ETH_STATS_T eth;
+ PCI_EEAI_STATS_T pci_eeai;
+ RAPIDIO_STATS_T rapidIo;
+ UTOPIA_STATS_T utopia;
+ HPI_STATS_T hpi;
+ } u;
+} BOOT_STATS_T;
+
+extern BOOT_STATS_T bootStats;
+
+/*******************************************************************************
+ * Definition: The magic start address, known to all modules
+ *******************************************************************************/
+extern volatile UINT32 *p_boot_entry_addr;
+
+#endif /* __TIBOOT_H__ */
+
+/* nothing past this point */
index d7d407e6ab92533d9afb3db971985be7c0d681ba..b5fbbc0f61f73643dd196b075d45f3cce939519e 100644 (file)
CSRC= c6474.c c6474init.c
else
ifeq ($(TARGET),c6474l)
- CSRC= c6474l.c
+ CSRC= c6474l.c c6474linit.c
else
ifeq ($(TARGET),c6457)
CSRC= c6457.c c6457init.c
ifeq ($(TARGET),c66x)
CSRC= c66x.c c66xinit.c c66xutil.c
else
- CSRC= c6472.c c6455.c c6474.c c6474l.c c6457.c c6472init.c c6455init.c c6474init.c c66x.c c66xinit.c c66xutil.c
+ CSRC= c6472.c c6455.c c6474.c c6474l.c c6457.c c6472init.c c6455init.c c6474linit.c c6474init.c c66x.c c66xinit.c c66xutil.c
endif
endif
endif
diff --git a/src/make/Makefile b/src/make/Makefile
index a6cddeb477d44ad31fc38b621df6ea73a06412b8..5ddc9cddfcdf76f2dc6eb942ca010a4d22741b97 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
#* make test_build
#*******************************************************************************************
-IBLS_C6X= c6455 c6472 c6474 c6457 c66x
-EVMS_C6X= evm_c6455 evm_c6472 evm_c6474
+IBLS_C6X= c6455 c6472 c6474 c6474l c6457 c66x
+EVMS_C6X= evm_c6455 evm_c6472 evm_c6474 evm_c6474l
# Excluding functions from the build reduces the I2C eeprom memory used and
SPI_DEFS+= SPI_ROM=$(SPI_ROM)
-.PHONY: all $(IBLS_C6X) evm_c6455 evm_c6472 evm_c6474 evm_c6457 evm_c6678_i2c evm_c6670_i2c
+.PHONY: all $(IBLS_C6X) evm_c6455 evm_c6472 evm_c6474 evm_c6474l evm_c6457 evm_c6678_i2c evm_c6670_i2c
.PHONY: test_c66x test_c6455 test_c6472 test_c6474 test_c6457 clean
cp -f ../util/i2cConfig/i2cparam_c6474_$(ENDIAN_SFX).out bin/i2cparam_0x50_c6474_$(ENDIAN_SFX)_0x200.out
evm_c6474l:
- make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 \
- COMPACT_I2C=yes ENDIAN_MODE=$(ENDIAN) CEXCLUDES='ELF COFF BIS MULTI_BOOT' I2C_SIZE_BYTES=0x8000 c6474
- cp -f ibl_c6474/i2crom.dat bin/i2crom_0x50_c6474l_$(ENDIAN_SFX).dat
- cp -f ibl_c6474/i2crom.bin bin/i2crom_0x50_c6474l_$(ENDIAN_SFX).bin
- cp -f ../util/i2cConfig/i2cparam_c6474_$(ENDIAN_SFX).out bin/i2cparam_0x50_c6474l_$(ENDIAN_SFX)_0x200.out
+ make -f makestg1 ARCH=c64x TARGET=c6474l I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=0x200 \
+ COMPACT_I2C=yes ENDIAN_MODE=$(ENDIAN) CEXCLUDES='ELF COFF BIS MULTI_BOOT' I2C_SIZE_BYTES=0x8000 c6474l
+ cp -f ibl_c6474l/i2crom.dat bin/i2crom_0x50_c6474l_$(ENDIAN_SFX).dat
+ cp -f ibl_c6474l/i2crom.bin bin/i2crom_0x50_c6474l_$(ENDIAN_SFX).bin
+ cp -f ../util/i2cConfig/i2cparam_c6474l_$(ENDIAN_SFX).out bin/i2cparam_0x50_c6474l_$(ENDIAN_SFX)_0x200.out
# The 6457 EVM
evm_c6457:
make -f makestg2 clean ARCH=c64x TARGET=c6472
make -f makestg2 cleant ARCH=c64x TARGET=c6472
make -f makestg2 cleant ARCH=c64x TARGET=c6474
+ make -f makestg2 cleant ARCH=c64x TARGET=c6474l
make -f makestg2 cleant ARCH=c64x TARGET=c6455
make -f makestg2 cleant ARCH=c64x TARGET=c6457
make -f makestg2 cleant ARCH=c64x TARGET=c66x
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6455
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6472
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6474
+ make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6474l
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6457
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c66x
make -C ../util/romparse clean
diff --git a/src/make/ibl_c6474l/i2crom.map.pre b/src/make/ibl_c6474l/i2crom.map.pre
--- /dev/null
@@ -0,0 +1,72 @@
+#include "iblcfg.h"
+; This file is run through the C preprocessor to get the build time layout information
+; The following values must be defined:
+; I2C_BUS_ADDR - The I2C bus address of the eeprom holding the ROM boot info and the layout info
+; INIT_EXE_FILE - The I2C blocked stage 1 of the ibl
+; EXE_FILE_1 - The I2C blocked stage 2 of the ibl, must be the little endian version
+; EXE_FILE_2 - The I2C blocked stage 2 of the ibl, must be the big endian version
+; PAD_FILE_ID_1 - This pad holds the IBL configuration structure for the little endian version
+; PAD_FILE_ID_2 - This pad holds the IBL configuration structure for the big endian version
+;
+; The section statement directs the ROM boot loader to load the initial endian independent
+; portion of the IBL
+section
+{
+ param_index = 1
+ boot_mode = 257
+ sw_pll = 20
+ options = 1
+
+ core_freq_mhz = 1000
+ i2c_clk_freq_khz = 100
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 200
+ exe_file = INIT_EXE_FILE
+}
+
+; The layout statement defines how the resulting I2C image is layed out. The base address
+; of this (given in the dev_addr) statement must be known to the initial IBL program
+; at compile time. The layout block is simple a group of 32 bit i2c addresses, so
+; the order of the exe_file and pad_file_id statements must be configured so as to
+; match the definition of struct iblI2cMap_t defined in ibl.h.
+layout
+{
+ dev_addr = IBL_CFG_I2C_MAP_TABLE_DATA_ADDR ; Defined in iblcfg.h
+ dev_addr_ext = I2C_BUS_ADDR
+ file_align = 0x80
+
+ exe_file = EXE_FILE_1
+ pad_file_id = PAD_FILE_ID_1
+
+
+ exe_file = EXE_FILE_2
+ pad_file_id = PAD_FILE_ID_2
+}
+
+; The pad statements simply provide space for the IBL configuration structures. It is valid to
+; have a single configuration structure which is used for both endian values.
+pad
+{
+ pad_file_id = 1
+ dev_addr = 0x200
+ dev_addr_ext = I2C_BUS_ADDR
+ len = 0x300
+}
+
+#if (PAD_FILE_ID_1 != PAD_FILE_ID_2)
+pad
+{
+ pad_file_id = 2
+ dev_addr = 0x500
+ dev_addr_ext = I2C_BUS_ADDR
+ len = 0x300
+}
+#endif
+
+
+
+
diff --git a/src/make/ibl_c6474l/ibl.cmd b/src/make/ibl_c6474l/ibl.cmd
--- /dev/null
@@ -0,0 +1,33 @@
+/************************************************************************************
+ * FILE PURPOSE: Define the memory usage of the ibl module for the c6474
+ ************************************************************************************
+ * FILE NAME: ibl.cmd
+ *
+ * DESCRIPTION: The memory placement for the IBL is defined
+ *
+ ************************************************************************************/
+
+/* In order to speed build time during debug, the object files are saved in
+ * both big and little endian format. The include file is generated by
+ * make to use the correct endian object files
+ */
+#include "ibl_objs.inc"
+
+
+/* Symbols from the 1st portion of the load, generated by the make process */
+#include "ibl_init_symbols.inc"
+
+/* Common memory and section areas between ibl_init and ibl */
+#include "ibl_common.inc"
+
+SECTIONS
+{
+ .cinit > TEXT
+ .const > TEXT
+ .text > TEXT
+ .switch > TEXT
+ .far > DATA
+ .bss > DATA
+
+}
+
diff --git a/src/make/ibl_c6474l/ibl.rmd b/src/make/ibl_c6474l/ibl.rmd
--- /dev/null
@@ -0,0 +1,11 @@
+-a
+-boot
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x0400, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c6474l/ibl_common.inc b/src/make/ibl_c6474l/ibl_common.inc
--- /dev/null
@@ -0,0 +1,42 @@
+/************************************************************************************
+ * FILE PURPOSE: Provide common memory and sections definitions for ibl_init and ibl
+ ************************************************************************************
+ * FILE NAME: ibl_common.inc
+ *
+ * DESCRIPTION: Defines the common memory map and section placement required
+ * to get ibl and ibl_init to work together in a two stage load
+ * process.
+ *************************************************************************************/
+
+-c
+-stack 0x800
+-heap 0x6000
+
+
+MEMORY
+{
+ TEXT_INIT : origin = 0x801000, length = 0x2800
+ TEXT : origin = 0x803800, length = 0xd800
+ STACK : origin = 0x811000, length = 0x0800
+ HEAP : origin = 0x811800, length = 0x6000
+ DATA_INIT : origin = 0x817800, length = 0x0400
+ DATA : origin = 0x817c00, length = 0x2c00
+ CFG : origin = 0x821800, length = 0x0300
+ STAT : origin = 0x821b00, length = 0x0200
+ CORE_1 : origin = 0x11800000, length = 4
+ CORE_2 : origin = 0x12800000, length = 4
+}
+
+
+SECTIONS
+{
+ .stack > STACK
+ .sysmem > HEAP
+
+ .ibl_config_table > CFG
+ .ibl_status_table > STAT
+
+ .idle_c1 > CORE_1
+ .idle_c2 > CORE_2
+}
+
diff --git a/src/make/ibl_c6474l/ibl_init.cmd b/src/make/ibl_c6474l/ibl_init.cmd
--- /dev/null
@@ -0,0 +1,31 @@
+/************************************************************************************
+ * FILE PURPOSE: Define the memory usage of the ibl module for the c6474
+ ************************************************************************************
+ * FILE NAME: ibl.cmd
+ *
+ * DESCRIPTION: The memory placement for the IBL is defined
+ *
+ ************************************************************************************/
+
+/* In order to speed build time during debug, the object files are saved in
+ * both big and little endian format. The include file is generated by
+ * make to use the correct endian object files
+ */
+#include "ibl_init_objs.inc"
+
+
+/* Common memory and section areas between ibl_init and ibl */
+#include "ibl_common.inc"
+
+
+SECTIONS
+{
+ .cinit > TEXT_INIT
+ .const > TEXT_INIT
+ .text > TEXT_INIT
+ .switch > TEXT_INIT
+ .far > DATA_INIT
+ .bss > DATA_INIT
+
+}
+
diff --git a/src/make/ibl_c6474l/ibl_init.rmd b/src/make/ibl_c6474l/ibl_init.rmd
--- /dev/null
@@ -0,0 +1,11 @@
+-a
+-boot
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x0400, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c6474l/ibl_init_image.rmd b/src/make/ibl_c6474l/ibl_init_image.rmd
--- /dev/null
@@ -0,0 +1,10 @@
+-a
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x801000, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c6474l/ibl_init_objs_template.inc b/src/make/ibl_c6474l/ibl_init_objs_template.inc
--- /dev/null
@@ -0,0 +1,19 @@
+/* ibl_init_objs_template.inc
+ *
+ * list of object files tagged with the endian field for replacement during make
+ */
+
+../main/c64x/make/iblinit.ENDIAN_TAG.oc
+../main/c64x/make/ibliniti2c.ENDIAN_TAG.oc
+../device/c64x/make/c6474linit.ENDIAN_TAG.oc
+../hw/c64x/make/pll.ENDIAN_TAG.oc
+../hw/c64x/make/i2c.ENDIAN_TAG.oc
+../interp/c64x/make/btblwrap.ENDIAN_TAG.oc
+../interp/c64x/make/btblpr.ENDIAN_TAG.oc
+../interp/c64x/make/gem.ENDIAN_TAG.oc
+
+
+
+
+
+
diff --git a/src/make/ibl_c6474l/ibl_objs_template.inc b/src/make/ibl_c6474l/ibl_objs_template.inc
--- /dev/null
@@ -0,0 +1,57 @@
+/* ibl_objs_template.inc
+ *
+ * list of object files tagged with the endian field for replacement during make
+ */
+
+../main/c64x/make/iblmain.ENDIAN_TAG.oc
+../device/c64x/make/c6474l.ENDIAN_TAG.oc
+../driver/c64x/make/timer.ENDIAN_TAG.oc
+../hw/c64x/make/t64.ENDIAN_TAG.oc
+../hw/c64x/make/psc.ENDIAN_TAG.oc
+../hw/c64x/make/emif31.ENDIAN_TAG.oc
+
+
+#ifndef EXCLUDE_BIS
+../interp/c64x/make/bis.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_COFF
+../interp/c64x/make/cload.ENDIAN_TAG.oc
+../interp/c64x/make/osal.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_BLOB
+../interp/c64x/make/blob.ENDIAN_TAG.oc
+#endif
+
+
+#ifndef EXCLUDE_ELF
+../interp/c64x/make/dload.ENDIAN_TAG.oc
+../interp/c64x/make/elfwrap.ENDIAN_TAG.oc
+../interp/c64x/make/dlw_client.ENDIAN_TAG.oc
+../interp/c64x/make/dload_endian.ENDIAN_TAG.oc
+../interp/c64x/make/ArrayList.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_ETH
+../ethboot/c64x/make/ethboot.ENDIAN_TAG.oc
+../driver/c64x/make/net.ENDIAN_TAG.oc
+../driver/c64x/make/arp.ENDIAN_TAG.oc
+../driver/c64x/make/ip.ENDIAN_TAG.oc
+../driver/c64x/make/udp.ENDIAN_TAG.oc
+../driver/c64x/make/stream.ENDIAN_TAG.oc
+../driver/c64x/make/bootp.ENDIAN_TAG.oc
+../driver/c64x/make/tftp.ENDIAN_TAG.oc
+../hw/c64x/make/cpmacdrv.ENDIAN_TAG.oc
+../hw/c64x/make/mdio.ENDIAN_TAG.oc
+../hw/c64x/make/sgmii.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_NAND_GPIO
+../nandboot/c64x/make/nandboot.ENDIAN_TAG.oc
+../driver/c64x/make/nand.ENDIAN_TAG.oc
+../ecc/c64x/make/3byte_ecc.ENDIAN_TAG.oc
+../hw/c64x/make/gpio.ENDIAN_TAG.oc
+../hw/c64x/make/nandgpio.ENDIAN_TAG.oc
+#endif
+
diff --git a/src/make/makestg1 b/src/make/makestg1
index 1dd12405cfc4ab047888086f3d15690b43499328..68a797f1bb9da555598f419bba1ca3ebc6e6f1e0 100644 (file)
--- a/src/make/makestg1
+++ b/src/make/makestg1
C64X_EXCLUDES=yes
endif
+ifeq ($(TARGET),c6474l)
+ C64X_EXCLUDES=yes
+endif
+
ifeq ($(C64X_EXCLUDES),yes)
ifeq (,$(findstring SPI, $(EXCLUDES)))