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raw | patch | inline | side by side (parent: dce2e84)
raw | patch | inline | side by side (parent: dce2e84)
| author | Sandeep Paulraj <s-paulraj@ti.com> | |
| Wed, 10 Aug 2011 00:40:16 +0000 (20:40 -0400) | ||
| committer | Sandeep Paulraj <s-paulraj@ti.com> | |
| Wed, 10 Aug 2011 00:40:16 +0000 (20:40 -0400) |
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| src/util/single-bin/build/Makefile | [new file with mode: 0644] | patch | blob |
| src/util/single-bin/iblcfg/device.c | [new file with mode: 0644] | patch | blob |
| src/util/single-bin/iblcfg/device.h | [new file with mode: 0644] | patch | blob |
| src/util/single-bin/iblcfg/iblConfig.c | [new file with mode: 0644] | patch | blob |
| src/util/single-bin/iblcfg/input.txt | [new file with mode: 0644] | patch | blob |
| src/util/single-bin/iblcfg/types.h | [new file with mode: 0644] | patch | blob |
diff --git a/src/util/single-bin/build/Makefile b/src/util/single-bin/build/Makefile
--- /dev/null
@@ -0,0 +1,67 @@
+###############################################################################
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+###############################################################################
+
+CC = gcc
+AR = ar
+
+###############################################################################
+# Set host specific default options
+###############################################################################
+LD_OPTS =
+C_OPTS =
+
+#RT_LIB = $(C_DIR)/lib/libc.a
+C_OPTS += -O2
+
+#LNK_OPTS += -i$(C_DIR)/lib -c $(RT_LIB)
+LNK_OPTS +=
+
+###############################################################################
+# List of modules and their files
+###############################################################################
+
+IBLCFG_EXE = iblConfig.out
+FILES = \
+ iblConfig.c \
+ device.c \
+ device.h \
+ types.h \
+
+OBJ_DIR = ./obj
+VPATH = ../iblcfg
+CLIB_INC = $(C_DIR)/include/
+
+HEADERS = $(filter %.h, $(FILES))
+INCL = -I$(CLIB_INC) $(patsubst %,-I%,$(VPATH))
+TARGET_TEMP = $(patsubst %,-D%,$(TARGET))
+DEFINE_TARGET = $(patsubst %,%_TARGET,$(TARGET_TEMP))
+
+OBJS = $(patsubst %.c,$(OBJ_DIR)/%.obj,$(filter %.c, $(FILES)))
+
+###############################################################################
+# Normal make process
+###############################################################################
+
+$(IBLCFG_EXE): $(OBJS)
+ $(CC) $(C_OPTS) $(OBJS) $(LNK_OPTS) -o $@
+ cp $@ $@.dbg
+
+$(OBJ_DIR)/%.obj: %.c $(HEADERS) $(OBJ_DIR)/.created
+ $(CC) -c $(C_OPTS) $(INCL) $(DEFINE_TARGET) $< -o $@
+
+$(OBJ_DIR)/.created:
+ mkdir -p $(OBJ_DIR)
+ touch $(OBJ_DIR)/.created
+
+
+###############################################################################
+# Cleanup
+###############################################################################
+clean:
+ -rm -rf ./obj/
+ -rm -rf $(IBLCFG_EXE)
+ -rm -rf *.dbg
+ -rm -rf *.out
+ -rm -rf *.bin
+
diff --git a/src/util/single-bin/iblcfg/device.c b/src/util/single-bin/iblcfg/device.c
--- /dev/null
@@ -0,0 +1,1144 @@
+/************************************************************************************
+ * FILE PURPOSE: C6455 Device Specific functions used in the 1st load stage
+ ************************************************************************************
+ * FILE NAME: c6455init.c
+ *
+ * DESCRIPTION: Implements the device specific functions for the IBL
+ *
+ * @file c6455.c
+ *
+ * @brief
+ * This file implements the device specific functions for the IBL
+ *
+ ************************************************************************************/
+#include "device.h"
+
+ibl_t c6455_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6455L;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 500 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
+
+ /* SGMII not present */
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 0;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
+
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,118);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* There is no e-fuse mac address. A value must be assigned */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 10;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 224;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 166;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 102;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 87;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 25;
+
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6474_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6474M;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* There is no port 1 on the 6474 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x26;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (13 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (13 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
+
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 10,218,109,35);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 10,218,109,196);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 10,218,109,1);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6474l_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6474L;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000e23;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* There is no port 1 on the 6474 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 5;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
+
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,118);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6457_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6457L;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
+
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000e21;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081021;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* There is no port 1 on the 6457 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 5;
+ ibl.mdioConfig.mdioClkDiv = 0xa5;
+ ibl.mdioConfig.interDelay = 3000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
+
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,115);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6472_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6472L;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+ /* SGMII not present */
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
+
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,113);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Leave the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '2';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ /* bootMode[2] not configured */
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6678_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6678L;
+
+ /* Main PLL: 100 MHz reference, 1GHz output */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
+ ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
+ ibl.pllConfig[ibl_DDR_PLL].mult = 12;
+ ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
+
+ /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_NET_PLL].prediv = 1;
+ ibl.pllConfig[ibl_NET_PLL].mult = 21;
+ ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050;
+
+
+ ibl.ddrConfig.configDdr = 1;
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
+
+
+ ibl.sgmiiConfig[0].configure = 1;
+ ibl.sgmiiConfig[0].adviseAbility = 1;
+ ibl.sgmiiConfig[0].control = 1;
+ ibl.sgmiiConfig[0].txConfig = 0x108a1;
+ ibl.sgmiiConfig[0].rxConfig = 0x700621;
+ ibl.sgmiiConfig[0].auxConfig = 0x41;
+
+ ibl.sgmiiConfig[1].configure = 1;
+ ibl.sgmiiConfig[1].adviseAbility = 1;
+ ibl.sgmiiConfig[1].control = 1;
+ ibl.sgmiiConfig[1].txConfig = 0x108a1;
+ ibl.sgmiiConfig[1].rxConfig = 0x700621;
+ ibl.sgmiiConfig[1].auxConfig = 0x41;
+
+ ibl.mdioConfig.nMdioOps = 0;
+
+ ibl.spiConfig.addrWidth = 24;
+ ibl.spiConfig.nPins = 5;
+ ibl.spiConfig.mode = 1;
+ ibl.spiConfig.csel = 2;
+ ibl.spiConfig.c2tdelay = 1;
+ ibl.spiConfig.busFreqMHz = 20;
+
+ ibl.emifConfig[0].csSpace = 2;
+ ibl.emifConfig[0].busWidth = 8;
+ ibl.emifConfig[0].waitEnable = 0;
+
+ ibl.emifConfig[1].csSpace = 0;
+ ibl.emifConfig[1].busWidth = 0;
+ ibl.emifConfig[1].waitEnable = 0;
+
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
+
+ ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Use the e-fuse value */
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
+ibl_t c6670_ibl_config(void)
+{
+ ibl_t ibl;
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_C6670L;
+
+ /* Main PLL: 122.88 MHz reference, 983 MHz output */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 16;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
+
+ /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
+ ibl.pllConfig[ibl_DDR_PLL].mult = 12;
+ ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
+
+ /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_NET_PLL].prediv = 1;
+ ibl.pllConfig[ibl_NET_PLL].mult = 17;
+ ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1044;
+
+
+ ibl.ddrConfig.configDdr = 1;
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
+
+
+ ibl.sgmiiConfig[0].configure = 1;
+ ibl.sgmiiConfig[0].adviseAbility = 1;
+ ibl.sgmiiConfig[0].control = 1;
+ ibl.sgmiiConfig[0].txConfig = 0x108a1;
+ ibl.sgmiiConfig[0].rxConfig = 0x700621;
+ ibl.sgmiiConfig[0].auxConfig = 0x41;
+
+ ibl.sgmiiConfig[1].configure = 1;
+ ibl.sgmiiConfig[1].adviseAbility = 1;
+ ibl.sgmiiConfig[1].control = 1;
+ ibl.sgmiiConfig[1].txConfig = 0x108a1;
+ ibl.sgmiiConfig[1].rxConfig = 0x700621;
+ ibl.sgmiiConfig[1].auxConfig = 0x51;
+
+ ibl.mdioConfig.nMdioOps = 0;
+
+ ibl.spiConfig.addrWidth = 24;
+ ibl.spiConfig.nPins = 5;
+ ibl.spiConfig.mode = 1;
+ ibl.spiConfig.csel = 2;
+ ibl.spiConfig.c2tdelay = 1;
+ ibl.spiConfig.busFreqMHz = 20;
+
+ ibl.emifConfig[0].csSpace = 2;
+ ibl.emifConfig[0].busWidth = 8;
+ ibl.emifConfig[0].waitEnable = 0;
+
+ ibl.emifConfig[1].csSpace = 0;
+ ibl.emifConfig[1].busWidth = 0;
+ ibl.emifConfig[1].waitEnable = 0;
+
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
+
+ ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Use the e-fuse value */
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
+
diff --git a/src/util/single-bin/iblcfg/device.h b/src/util/single-bin/iblcfg/device.h
--- /dev/null
@@ -0,0 +1,917 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/********************************************************************************************************
+ * FILE PURPOSE: IBL configuration and control definitions
+ ********************************************************************************************************
+ * FILE NAME: ibl.h
+ *
+ * DESCRIPTION: Defines the data structure used to handle initial configuration and control
+ * of the ibl. This data structure resides at a fixed location in the device memory
+ * map. It is initially populated either during the rom boot. The table can be
+ * over-written during the ibl process to redirect the boot. For example the ibl
+ * can initially load from an i2c which repopulates this table with parameters
+ * for an ethernet boot.
+ *
+ * @file ibl.h
+ *
+ * @brief
+ * This file defines the configuration and control of the IBL
+ *
+ *
+ ********************************************************************************************************/
+#ifndef IBL_H
+#define IBL_H
+
+#include "types.h"
+
+
+#define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
+
+
+/**
+ * @brief
+ * The version number, 1.0.0.9
+ */
+#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,9)
+
+#define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
+ array[1]=(i1); \
+ array[2]=(i2); \
+ array[3]=(i3)
+/**
+ * @defgroup iblBootModes Defines the boot modes supported by the IBL
+ *
+ * @ingroup iblBootModes
+ * @{
+ *
+ * @def ibl_BOOT_MODE_TFTP */
+#define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */
+
+ /* @def ibl_BOOT_MODE_NAND */
+#define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */
+
+/* @def ibl_BOOT_MODE_NOR */
+#define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */
+
+/* @def ibl_BOOT_MODE_NONE */
+#define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */
+
+/* @} */
+
+/**
+ * @brief
+ * Define the number of different boot modes which can be configured for
+ * a single execution of the IBL.
+ */
+#define ibl_N_BOOT_MODES 3
+
+/* Information used to make generate a bootp request */
+/**
+ * @brief
+ * Defines parameters used for making a bootp request
+ *
+ * @details
+ * The bootp request parameters are created from these fields
+ */
+typedef struct iblBootp_s
+{
+ uint8 hwAddress[6]; /**< The hardware (mac) address of this device. If set to 0
+ the ibl will values from e-fuse */
+
+ uint8 ipDest[4]; /**< The IP address of this device. This is typically set
+ to IP broadcast */
+
+} iblBootp_t;
+
+
+/**
+ * @brief
+ * This structure contains information used for tftp boot.
+ *
+ * @details These fields are typically filled in by the bootp packet, but
+ * can be provided if bootp will not be used.
+ */
+typedef struct iblEthBootInfo_s
+{
+ uint8 ipAddr[4]; /**< The IP address of this device */
+ uint8 serverIp[4]; /**< The IP address of the tftp server */
+ uint8 gatewayIp[4]; /**< The IP address of the gateway */
+ uint8 netmask[4]; /**< The IP netmask */
+ uint8 hwAddress[6]; /**< The hardware (mac) address of this device */
+ char8 fileName[64]; /**< The file name to load */
+
+} iblEthBootInfo_t;
+
+
+/**
+ * @def ibl_ETH_PORT_FROM_RBL
+ */
+#define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
+ during the ROM boot load process. */
+
+/**
+ * @def ibl_PORT_SWITCH_ALL
+ */
+#define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
+ all ports on the subsystem should be configured */
+
+
+/**
+ * @defgroup iblBootFormats
+ *
+ * @ingroup iblBootFormats
+ * @{
+ */
+#define ibl_BOOT_FORMAT_AUTO 0 /**< Auto determine the boot format from the data */
+#define ibl_BOOT_FORMAT_NAME 1 /**< Determines the boot format based on file name (bootp/tftp only) */
+#define ibl_BOOT_FORMAT_BIS 2 /**< Boot TI AIS format */
+#define ibl_BOOT_FORMAT_COFF 3 /**< Boot a COFF file */
+#define ibl_BOOT_FORMAT_ELF 4 /**< Boot an ELF file */
+#define ibl_BOOT_FORMAT_BBLOB 5 /**< Boot a binary blob */
+#define ibl_BOOT_FORMAT_BTBL 6 /**< Boot a TI boot table file */
+
+/* @} */
+
+/**
+ * @defgroup iblPeriphPriority Defines the boot sequence
+ *
+ * @ingroup iblPeriphPriority
+ * @{
+ * @def ibl_LOWEST_PRIORITY
+ */
+#define ibl_LOWEST_PRIORITY 10 /**< The lowest priority assignable to a peripheral for boot */
+
+/**
+ * @def ibl_HIGHEST_PRIORITY
+ */
+#define ibl_HIGHEST_PRIORITY 1 /**< The highest priority assignable to a peripheral for boot */
+
+/**
+ * @def ibl_DEVICE_NOBOOT
+ */
+#define ibl_DEVICE_NOBOOT 20 /**< Indicates that the device is not to be used for boot */
+
+/* @} */
+
+
+/**
+ * @brief
+ * Emif controller 3.1 configuration
+ *
+ * @details
+ * The paramters are directly placed into the emif controller
+ */
+typedef struct iblEmif3p1_s
+{
+ uint32 sdcfg; /**< SD configuration register */
+ uint32 sdrfc; /**< Refresh timing register */
+ uint32 sdtim1; /**< DDR timing register 1 */
+ uint32 sdtim2; /**< DDR timing register 2 */
+ uint32 dmcctl; /**< CAS match timing */
+
+} iblEmif3p1_t;
+
+
+/**
+ * @brief
+ * Emif controller 4.0 configuration
+ *
+ * @details
+ * The parameters are placed directly into the emif controller
+ */
+typedef struct iblEmif4p0_s
+{
+ uint32 registerMask; /**< Identifies which registers will be configured */
+ uint32 sdRamConfig; /**< SDRAM Config Register */
+ uint32 sdRamConfig2; /**< SDRAM Config2 Register */
+ uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
+ uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
+ uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
+ uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
+ uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
+ uint32 powerManageCtl; /**< Power Management Control Register */
+ uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
+ uint32 performCountCfg; /**< Performance Counter Config Register */
+ uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
+ uint32 readIdleCtl; /**< Read Idle Control Register */
+ uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
+ uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
+ uint32 tempAlterCfg; /**< Temperature Alert Config Register */
+ uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
+ uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
+ uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
+ uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
+ uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
+ uint32 eccCtl; /**< ECC Control Register */
+ uint32 eccRange1; /**< ECC Address Range 1 Register */
+ uint32 eccRange2; /**< ECC Address Range 2 Register */
+ uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
+
+} iblEmif4p0_t;
+
+
+/**
+ * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
+ *
+ * @ingroup iblEmif4Select
+ * @{
+ * @def ibl_EMIF4_ENABLE_sdRamConfig
+ */
+#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
+
+/** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
+#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
+
+/** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
+#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
+#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
+#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
+
+/** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
+#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
+
+/** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
+#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
+
+/** @def ibl_EMIF4_ENABLE_powerManageCtl */
+#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
+
+/** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
+#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
+
+/** @def ibl_EMIF4_ENABLE_performCountCfg */
+#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
+
+/** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
+#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
+
+/** @def ibl_EMIF4_ENABLE_readIdleCtl */
+#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
+#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
+
+/** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
+#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
+
+/** @def ibl_EMIF4_ENABLE_tempAlterCfg */
+#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
+
+/** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
+#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
+
+/** @def ibl_EMIF4_ENABLE_priClassSvceMap */
+#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
+
+/** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
+
+/** @def ibl_EMIF4_ENABLE_eccCtl */
+#define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
+
+/** @def ibl_EMIF4_ENABLE_eccRange1 */
+#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
+
+/** @def ibl_EMIF4_ENABLE_eccRange2 */
+#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
+
+/** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
+#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
+
+/** @def ibl_BOOT_EMIF4_ENABLE_ALL */
+#define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
+
+/* @} */
+
+
+/**
+ * @defgroup iblEmifType Defines the EMIF4 type on a device
+ *
+ * @ingroup iblEmifType
+ * @{
+ */
+/** @def ibl_EMIF_TYPE_31 */
+#define ibl_EMIF_TYPE_31 31
+
+/** @def ibl_EMIF_TYPE_40 */
+#define ibl_EMIF_TYPE_40 40
+
+/* @} */
+
+/**
+ * @brief
+ * This structure is used to configure the DDR interface
+ *
+ * @details
+ * The DDR configuration parameters are setup
+ *
+ */
+typedef struct idblDdr_s
+{
+ bool configDdr; /**< Set to non-zero to enable EMIF configuration */
+
+ union {
+
+ iblEmif3p1_t emif3p1; /**< Configuration of devices with emif controller version 3.1 */
+ iblEmif4p0_t emif4p0; /**< Configuration of devices with emif controller version 4.0 */
+ } uEmif;
+
+} iblDdr_t;
+
+/**
+ * @brief
+ * This structure is used to identify binary blob load parameters.
+ *
+ * @details
+ * Since binary blob is formatless the start address, size and branch to address
+ * can be specified. In the case of network boot, boot will terminate when no
+ * more data is received (or timed out), even if the size is not reached.
+ */
+typedef struct iblBinBlob_s
+{
+ uint32 startAddress; /**< Where the loaded data is placed */
+ uint32 sizeBytes; /**< How much data to load */
+ uint32 branchAddress; /**< Where to branch to when the load is complete */
+
+} iblBinBlob_t;
+
+/**
+ * @brief
+ * This structure is used to control the operation of the ibl ethernet boot.
+ *
+ * @details
+ * The ethernet port and bootp request are controlled through this structure.
+ */
+typedef struct iblEth_s
+{
+ bool doBootp; /**< If true a bootp request is generated. If false the @ref iblEthBootInfo_t
+ table must be populated before the ibl begins execution */
+ bool useBootpServerIp; /**< If TRUE then the server IP received from the bootp server
+ is used, if FALSE the one in the ethInfo field is used */
+ bool useBootpFileName; /**< If TRUE then the file name received from the bootp server
+ is used, if FALSE the one in the ethInfo field is used */
+ int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+
+ iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+ iblEthBootInfo_t ethInfo; /**< Low level ethernet information */
+
+} iblEth_t;
+
+
+/**
+ * @brief
+ * This structure is used to control the operation of the ibl sgmii ports
+ *
+ * @details
+ * The physical register configuration is provided
+ */
+typedef struct iblSgmii_s
+{
+ bool configure; /**< Set to false to disable configuration */
+ uint32 adviseAbility; /**< The advise ability register */
+ uint32 control; /**< The control register */
+ uint32 txConfig; /**< Serdes Tx config */
+ uint32 rxConfig; /**< Serdes Rx config */
+ uint32 auxConfig; /**< Serdes Aux config */
+
+} iblSgmii_t;
+
+
+/**
+ * @def ibl_N_ETH_PORTS
+ */
+#define ibl_N_ETH_PORTS 2 /**< The number of ethernet port configurations available */
+
+/**
+ * @def ibl_N_MDIO_CFGS
+ */
+#define ibl_N_MDIO_CFGS 16 /**< The maximum number of mdio configurations */
+
+
+/**
+ * @brief
+ * This structure is used to configure phys through the mdio interface
+ *
+ * @details
+ * Defines optional configuration through MDIO.
+ *
+ * The mdio transaction values are mapped as follows:
+ *
+ * /-------------------------------------------------------------\
+ * | 31 | 30 | 29 26 | 25 21 | 20 16 | 15 0|
+ * | rsvd | write | rsvd | register | phy addr | data |
+ * \-------------------------------------------------------------/
+ */
+typedef struct iblMdio_s
+{
+ int16 nMdioOps; /**< The number of mdio writes to perform */
+ uint16 mdioClkDiv; /**< The divide down of the mac clock which drives the mdio */
+
+ uint32 interDelay; /**< The number of cpu cycles to wait between mdio writes */
+
+ uint32 mdio[ibl_N_MDIO_CFGS]; /* The MDIO transactions */
+
+} iblMdio_t;
+
+/**
+ * @def ibl_N_ECC_BYTES
+ */
+#define ibl_N_ECC_BYTES 10 /**< The number of ECC bytes to be computed for each page */
+
+/**
+ * @def ibl_N_BAD_BLOCK_MARKER
+ */
+#define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
+
+/**
+ * @brief
+ * This structure defines the physical parameters of the NAND device
+ */
+typedef struct nandDevInfo_s
+{
+ uint32 busWidthBits; /**< 8 or 16 bit bus width */
+ uint32 pageSizeBytes; /**< The size of each page */
+ uint32 pageEccBytes; /**< Number of ecc bytes in each page */
+ uint32 pagesPerBlock; /**< The number of pages in each block */
+ uint32 totalBlocks; /**< The total number of blocks in a device */
+
+ uint32 addressBytes; /**< Number of bytes in the address */
+ bool lsbFirst; /**< Set to true if the LSB is output first, otherwise msb is first */
+ uint32 blockOffset; /**< Address bits which specify the block number */
+ uint32 pageOffset; /**< Address bits which specify the page number */
+ uint32 columnOffset; /**< Address bits which specify the column number */
+
+ uint8 eccBytesIdx[ibl_N_ECC_BYTES];
+ /**< Index of each ECC byte in each page data */
+ uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
+ /**< Index of bad block marker in each page data */
+
+ uint8 resetCommand; /**< The command to reset the flash */
+ uint8 readCommandPre; /**< The read command sent before the address */
+ uint8 readCommandPost; /**< The read command sent after the address */
+ bool postCommand; /**< If TRUE the post command is sent */
+
+} nandDevInfo_t;
+
+
+/**
+ * @def ibl_N_ENDIANS
+ */
+#define ibl_N_ENDIANS 2 /**< The number of endians supported */
+
+#define ibl_ENDIAN_BIG 0 /**< Big endian */
+#define ibl_ENDIAN_LITTLE 1 /**< Little endian */
+
+/**
+ * @def ibl_N_IMAGES
+ */
+#define ibl_N_IMAGES 2 /**< The number of boot images supported on the same device */
+
+/**
+ * @brief
+ * This structure is used to control the operation of the NAND boot
+ *
+ */
+typedef struct iblNand_s
+{
+
+ int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+ uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address of each image for booting */
+ int32 interface; /**< The nand interface @ref iblPmemf */
+ iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+
+ nandDevInfo_t nandInfo; /** Low level device info */
+
+} iblNand_t;
+
+/**
+ * @brief
+ * Nor boot configuration.
+ */
+typedef struct iblNor_s
+{
+ int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
+ uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address for booting */
+ int32 interface; /**< The nor interface. @ref iblPmemIf */
+ iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
+
+} iblNor_t;
+
+extern uint32 iblEndianIdx;
+extern uint32 iblImageIdx;
+
+/**
+ * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
+ * valid for all devices
+ *
+ * @ingroup iblPmemIf
+ * @{
+ */
+
+/** @def ibl_PMEM_IF_GPIO - GPIO interface */
+#define ibl_PMEM_IF_GPIO 0
+
+/** @def ibl_PMEM_IF_CHIPSEL_2 */
+#define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
+
+/** @def ibl_PMEM_IF_CHIPSEL_3 */
+#define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
+
+/** @def ibl_PMEM_IF_CHIPSEL_4 */
+#define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
+
+/** @def ibl_PMEM_IF_CHIPSEL_5 */
+#define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
+
+/** @def ibl_PMEM_IF_SPI */
+#define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
+
+/* @} */
+
+
+/**
+ * @brief
+ * EMIF (nand/nor) configuration
+ */
+typedef struct iblEmif_s {
+
+ int16 csSpace; /**< Chip select space, @ref iblPmemIf */
+ int16 busWidth; /**< Bus width, bits */
+ bool waitEnable; /**< Valid only for NOR devices */
+
+} iblEmif_t;
+
+/**
+ * @brief
+ * The maximum number of chip select spaces for emif boot (not ddr) configuration
+ */
+#define ibl_MAX_EMIF_PMEM 2
+
+
+/**
+ * @brief
+ * SPI configuration used for either NOR or NAND
+ */
+typedef struct iblSpi_s
+{
+ int16 addrWidth; /**< 16 or 24 are the only valid values */
+ int16 nPins; /**< 4 or 5 are the only valid values */
+ int16 mode; /**< Clock / data polarities (valid values 0-3) */
+ int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
+ uint16 c2tdelay; /**< Setup time between chip select and the transaction */
+ uint16 busFreqMHz; /**< Bus speed */
+
+} iblSpi_t;
+
+
+
+/**
+ * @brief
+ * This structure is used to control the programming of the device PLL
+ *
+ * @details
+ * The system PLLs are optionally configured
+ */
+typedef struct iblPll_s {
+
+ bool doEnable; /**< If true the PLL is configured */
+
+ Uint32 prediv; /**< The pll pre-divisor */
+ Uint32 mult; /**< The pll multiplier */
+ Uint32 postdiv; /**< The pll post divider */
+
+ Uint32 pllOutFreqMhz; /**< The resulting output frequency, required for timer setup */
+
+} iblPll_t;
+
+
+/**
+ * @defgroup iblPllNum
+ *
+ * @ingroup iblPllNum
+ * @{
+ *
+ * @def ibl_MAIN_PLL
+ */
+#define ibl_MAIN_PLL 0 /**< The main cpu pll */
+
+/**
+ * @def ibl_DDR_PLL
+ */
+#define ibl_DDR_PLL 1 /**< The ddr pll */
+
+/**
+ * @def ibl_NET_PLL
+ */
+#define ibl_NET_PLL 2 /**< The network pll */
+
+/**
+ * @def the number of PLL configuration entries in the table
+ */
+#define ibl_N_PLL_CFGS (ibl_NET_PLL + 1)
+
+/* @} */
+
+
+/**
+ * @def iblBoot_t
+ * Configures an ibl boot attempt
+ *
+ * @details
+ * The ibl allows for the configuration for multiple boot attempts. This structure is
+ * used to configure the ibl boot attempt.
+ */
+typedef struct iblBoot_s
+{
+
+ int32 bootMode; /**< Identifies the boot mode @ref iblBootModes */
+
+ uint32 priority; /**< The boot priority. @ref iblPeriphPriority */
+ int32 port; /**< The port to use, or @ref ibl_PORT_FROM_RBL */
+
+ union {
+
+ iblEth_t ethBoot; /**< Ethernet boot configuration. @ref iblEth_t */
+
+ iblNand_t nandBoot; /**< NAND boot configuration @ref iblNand_t */
+
+ iblNor_t norBoot; /**< NOR boot configuration @ref iblNor_t */
+
+ } u;
+
+} iblBoot_t;
+
+
+/**
+ * @def ibl_MAGIC_VALUE
+ */
+#define ibl_MAGIC_VALUE 0xCEC11EBC /**< Indicates that the configuration table is valid */
+
+/**
+ * @def ibl_EVM_TYPE
+ */
+#define ibl_EVM_C6455L 0x10 /**< C6455 Low Cost EVM */
+#define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
+#define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
+#define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
+#define ibl_EVM_C6474M 0x41 /**< C6474 Mez EVM */
+#define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
+#define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
+
+
+/**
+ * @brief
+ * The main configuration/control structure for the ibl
+ *
+ * @details
+ * The operation of the ibl is configured/controlled based on the values in this structure.
+ * This structure resides at a fixed location in the memory map. It can be changed during
+ * the boot operation itself by loading new values into it, but these changes must occur
+ * as part of the boot process itself (not through an asynchronous write through a master
+ * peripheral).
+ *
+ * Each boot mode is assigned a priority, with lower values indicating a higher
+ * priority. The lowest valid priority is @ref ibl_LOWEST_BOOT_PRIORITY, and the value
+ * @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral.
+ */
+typedef struct ibl_s
+{
+ uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
+
+ iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
+
+ iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
+
+ iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
+
+ iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
+
+ iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
+
+ iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
+
+ iblBoot_t bootModes[ibl_N_BOOT_MODES]; /**< Boot configuration */
+
+ uint16 iblEvmType; /**< @ref ibl_EVM_TYPE */
+
+ uint16 chkSum; /**< Ones complement checksum over the whole config structure */
+
+} ibl_t;
+
+
+extern ibl_t ibl;
+
+
+/**
+ * @defgroup iblActiveDevice
+ *
+ * @ingroup iblActiveDevice
+ * @{
+ * @def ibl_ACTIVE_DEVICE_ETH
+ */
+#define ibl_ACTIVE_DEVICE_ETH 100 /**< Data received through an ethernet interface */
+
+/**
+ * @def ibl_ACTIVE_DEVICE_EMIF
+ */
+#define ibl_ACTIVE_DEVICE_EMIF 101 /**< Data read through an EMIF interface */
+
+/**
+ * @def ibl_ACTIVE_DEVICE_I2C
+ */
+#define ibl_ACTIVE_DEVICE_I2C 102 /**< Data read through an I2C interface */
+
+/**
+ * @def ibl_ACTIVE_DEVICE_SPI
+ */
+#define ibl_ACTIVE_DEVICE_SPI 103 /**< Data read through an SPI interface */
+
+/* @} */
+
+
+/**
+ * @defgroup iblFailCode
+ *
+ * @ingroup iblFailCode
+ * @{
+ * @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
+ */
+#define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 /**< Invalid i2c eeprom address encountered */
+
+/**
+ * @def ibl_FAIL_CODE_BTBL_FAIL
+ */
+#define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
+
+/**
+ * @def ibl_FAIL_CODE_PA
+ */
+#define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
+
+
+/**
+ * @def ibl_FAIL_CODE_SPI_PARAMS
+ */
+#define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_INIT_DEVICE
+ */
+#define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 /**< Second stage boot device specified is invalid */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_SPI_ADDRESS
+ */
+#define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 /**< Invalid data address specified on SPI */
+
+/**
+ * @def ibl_FAIL_CODE_PERIPH_POWER_UP
+ */
+#define ibl_FAIL_CODE_PERIPH_POWER_UP 706 /**< Boot peripheral failed to power up */
+
+/**
+ * @def ibl_FAIL_CODE_INVALID_NAND_PERIPH
+ */
+#define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 /**< Invalid nand boot peripheral specified */
+
+/**
+ * @def ibl_FAIL_CODE_NO_EMIF_CFG
+ */
+#define ibl_FAIL_CODE_NO_EMIF_CFG 708 /**< No emif configuration found to match specified cs space */
+
+/**
+ * @def ibl_FAIL_CODE_EMIF_CFG_FAIL
+ */
+#define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 /**< Hardware setup of emif failed */
+
+ /* @} */
+
+
+/**
+ * @brief
+ * Provide status on the boot operation
+ *
+ * @details
+ * Run time status of the IBL is provided to aid in debugging
+ *
+ */
+typedef struct iblStatus_s
+{
+ uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
+
+ uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
+
+ uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
+
+ uint32 i2cRetries; /**< Count of I2C read retries */
+ uint32 i2cDataRetries; /**< Number of retries while reading block data from the i2c */
+
+ uint32 spiRetries; /**< Count of SPI read retries */
+ uint32 spiDataRetries; /**< Number of retries while reading block data from the spi */
+
+ uint32 magicRetries; /**< Count of I2C/SPI re-reads because the magic number was incorrect */
+ uint32 mapSizeFail; /**< Number of times an invalid map table size was read from the i2c/spi */
+ uint32 mapRetries; /**< Number of times the checksum failed on the read of the i2c/spi map */
+
+ int32 heartBeat; /**< An increasing value as long as the boot code is running */
+
+ int32 activeBoot; /**< Describes the active boot mode @ref iblBootModes */
+ int32 activeDevice; /**< Describes the active boot peripheral device @ref iblActiveDevice */
+ int32 activeFileFormat; /**< Describes the format being decoded */
+
+ uint32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
+ uint32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
+
+ uint32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
+
+ uint32 exitAddress; /**< If non-zero the IBL exited and branched to this address */
+
+ iblEthBootInfo_t ethParams; /**< Last ethernet boot attemp parameters */
+
+} iblStatus_t;
+
+extern iblStatus_t iblStatus;
+
+
+/**
+ * @brief
+ * The ibl boot map structure
+ *
+ * @details
+ * The ibl boot device contains a structure which identifies the location of the big and little
+ * endian ibl images on the external device.
+ */
+typedef struct iblBootMap_s
+{
+ uint16 length; /**< Size of the structure in bytes */
+ uint16 chkSum; /**< Value which makes the ones complement checksum over the block equal to 0 or -0 */
+
+ uint32 addrLe; /**< Base address of the boot tables for the little endian image */
+ uint32 configLe; /**< Base address of the ibl structure for use with the little endian image */
+
+ uint32 addrBe; /**< Base address of the boot tables for the big endian image */
+ uint32 configBe; /**< Base address of the ibl structure for use with the big endian image */
+
+} iblBootMap_t;
+
+
+ibl_t c6455_ibl_config(void);
+ibl_t c6474_ibl_config(void);
+ibl_t c6474l_ibl_config(void);
+ibl_t c6457_ibl_config(void);
+ibl_t c6472_ibl_config(void);
+ibl_t c6678_ibl_config(void);
+ibl_t c6670_ibl_config(void);
+
+
+
+
+
+#endif /* IBL_H */
diff --git a/src/util/single-bin/iblcfg/iblConfig.c b/src/util/single-bin/iblcfg/iblConfig.c
--- /dev/null
@@ -0,0 +1,206 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <arpa/inet.h>
+#include "device.h"
+
+#define TRUE 1
+#define FALSE 0
+#define MAX_LINE_LENGTH 40
+char *input_file = "input.txt";
+
+/* Parameters defined in the input_file */
+#define FILE_NAME "file_name"
+#define DEVICE_ID "device"
+#define OFFSET_ADDR "offset"
+
+char file_name[MAX_LINE_LENGTH];
+uint32_t device_id;
+uint32_t offset;
+
+#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
+typedef ibl_t (*ibl_config_fn)(void);
+
+int main (void)
+{
+ ibl_t ibl_params;
+ FILE *fp;
+ int ret;
+ ibl_config_fn cfg[] = {
+ [1] = &c6455_ibl_config,
+ [2] = &c6474_ibl_config,
+ [3] = &c6474l_ibl_config,
+ [4] = &c6457_ibl_config,
+ [5] = &c6472_ibl_config,
+ [6] = &c6678_ibl_config,
+ [7] = &c6670_ibl_config,
+ };
+ int ncfgs = ARRAY_SIZE(cfg);
+
+ fp = fopen(input_file, "r");
+ if (fp == NULL)
+ {
+ printf("Error in opening %s input file\n", input_file);
+ return;
+ }
+
+ ret = parse_input_file(fp);
+ fclose (fp);
+
+ if (ret == FALSE)
+ {
+ printf("Error in parsing %s input file\n", input_file);
+ return;
+ }
+
+
+ fp = fopen (file_name, "r+");
+ if (fp == NULL)
+ {
+ printf ("Failed to open file %s\n", file_name);
+ return;
+ }
+
+ printf ("Opened file %s\n", file_name);
+
+ if (fseek(fp, offset, SEEK_SET)) {
+ fclose(fp);
+ return -1;
+ }
+
+ if (device_id > 0 && device_id < ncfgs)
+ ibl_params = (*cfg[device_id])();
+
+ if (fwrite((void*)&ibl_params, sizeof(ibl_t), 1, fp) != 1) {
+ fclose(fp);
+ return -1;
+ }
+
+ fclose(fp);
+}
+
+int32_t
+xtoi
+(
+ char *xs,
+ uint32_t *result
+)
+{
+ uint32_t szlen = strlen(xs);
+ int32_t i, xv, fact;
+
+ if (szlen > 0)
+ {
+ /* Converting more than 32bit hexadecimal value? */
+ if (szlen>8) return 2; /* exit */
+
+ /* Begin conversion here */
+ *result = 0;
+ fact = 1;
+
+ /* Run until no more character to convert */
+ for(i=szlen-1; i>=0 ;i--)
+ {
+ if (isxdigit(*(xs+i)))
+ {
+ if (*(xs+i)>=97)
+ {
+ xv = ( *(xs+i) - 97) + 10;
+ }
+ else if ( *(xs+i) >= 65)
+ {
+ xv = (*(xs+i) - 65) + 10;
+ }
+ else
+ {
+ xv = *(xs+i) - 48;
+ }
+ *result += (xv * fact);
+ fact *= 16;
+ }
+ else
+ {
+ // Conversion was abnormally terminated
+ // by non hexadecimal digit, hence
+ // returning only the converted with
+ // an error value 4 (illegal hex character)
+ return 4;
+ }
+ }
+ return 0;
+ }
+
+ // Nothing to convert
+ return 1;
+}
+
+int parse_input_file(FILE *fp)
+{
+ char line[MAX_LINE_LENGTH];
+ char tokens[] = " :=;\n\r";
+ char *key, *data;
+
+ memset(line, 0, MAX_LINE_LENGTH);
+
+ fgets(line, MAX_LINE_LENGTH, fp);
+ key = (char *)strtok(line, tokens);
+ data = (char *)strtok(NULL, tokens);
+
+ if(strlen(data) == 0)
+ {
+ return FALSE;
+ }
+
+ if(strcmp(key, FILE_NAME) != 0)
+ {
+ return FALSE;
+ }
+
+ strcpy (file_name, data);
+
+ fgets(line, MAX_LINE_LENGTH, fp);
+ key = (char *)strtok(line, tokens);
+ data = (char *)strtok(NULL, tokens);
+
+ if(strlen(data) == 0)
+ {
+ return FALSE;
+ }
+
+ if(strcmp(key, DEVICE_ID) != 0)
+ {
+ return FALSE;
+ }
+
+ device_id = (uint32_t)atoi(data);
+
+ fgets(line, MAX_LINE_LENGTH, fp);
+ key = (char *)strtok(line, tokens);
+ data = (char *)strtok(NULL, tokens);
+
+ if(strlen(data) == 0)
+ {
+ return FALSE;
+ }
+
+ if(strcmp(key, OFFSET_ADDR) != 0)
+ {
+ return FALSE;
+ }
+
+ if ((data[0] == '0') && (data[1] == 'x' || data[1] == 'X'))
+ {
+ if (xtoi (&data[2], &offset) != 0)
+ {
+ return FALSE;
+ }
+ }
+ else
+ {
+ offset = (uint32_t)atoi(data);
+ }
+
+ return TRUE;
+}
+
diff --git a/src/util/single-bin/iblcfg/input.txt b/src/util/single-bin/iblcfg/input.txt
--- /dev/null
@@ -0,0 +1,3 @@
+file_name = ibl.bin
+device = 1
+offset = 0x200
diff --git a/src/util/single-bin/iblcfg/types.h b/src/util/single-bin/iblcfg/types.h
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+#ifndef _TYPES_H
+#define _TYPES_H
+/*******************************************************************************
+ * FILE PURPOSE: DSP specific C type definitions.
+ *******************************************************************************
+ * FILE NAME: ibl_types.h
+ *
+ * DESCRIPTION: Defines general use types for DSP.
+ *
+ * @file ibl_types.h
+ *
+ * @brief
+ * This file provides architecture specific typedefs
+ *
+ ******************************************************************************/
+
+
+#include <stdlib.h> /* Defines NULL */
+
+/* a signed 16-bit integer */
+typedef short int16;
+typedef unsigned short uint16;
+
+typedef int int32;
+typedef unsigned int uint32;
+
+typedef char char8;
+typedef unsigned char uchar8;
+
+typedef char int8;
+typedef unsigned char uint8;
+
+
+typedef unsigned char word;
+
+typedef short BOOL;
+typedef short bool;
+typedef short Bool;
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+
+/* tistdtypes.h types used from the emac driver */
+typedef unsigned char Uint8;
+typedef char Int8;
+typedef int Int32;
+typedef unsigned short Uint16;
+typedef unsigned int Uint32;
+
+/* TI boot types */
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef short SINT16;
+typedef unsigned int UINT32;
+typedef int SINT32;
+
+
+/* Types from evm driver */
+typedef volatile unsigned int VUint32;
+typedef volatile unsigned char VUint8;
+
+/* Types from the ethernet driver */
+typedef unsigned int IPN;
+
+#endif /* ibl_types.h */