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raw | patch | inline | side by side (parent: 291b54e)
raw | patch | inline | side by side (parent: 291b54e)
author | Sandeep Nair <sandeep_n@ti.com> | |
Fri, 17 Jun 2011 22:19:57 +0000 (18:19 -0400) | ||
committer | Sandeep Nair <sandeep_n@ti.com> | |
Fri, 17 Jun 2011 22:19:57 +0000 (18:19 -0400) |
doc/README.txt | patch | blob | history | |
src/device/c66x/c66xinit.c | patch | blob | history | |
src/device/c66x/target.h | patch | blob | history | |
src/driver/nand/nand.c | patch | blob | history | |
src/make/ibl_c66x/i2crom.map.pre | patch | blob | history | |
src/make/setupenv.bat | [deleted file] | patch | blob | history |
diff --git a/doc/README.txt b/doc/README.txt
index 2aedf9a6686372356645237f53b896edc3a919ca..0ae550200f03f6248411378b997cbd280d853b22 100644 (file)
--- a/doc/README.txt
+++ b/doc/README.txt
=====================================================
C6x Intermediate Bootloader (IBL)
-Version: 1.0.0.5
-May 2011
+Version: 1.0.0.6
+June 2011
=====================================================
This directory contains the following documents:
index deae692f3c2f42e578ce33024915ec02ced341b6..6488f1eb30721c44b5cfe2d2f08c73307f25a0ac 100644 (file)
*(volatile unsigned int *)(SMEDCC) |= 0x40000000; //Set ECM(bit30)=1
}
+#ifdef IBL_ENABLE_PCIE_WORKAROUND
+
+/* undocumented register in data manual
+ * Bit 0 of this register is supposed to give the status of PCIe PLL lock*/
+#define PCIE_STS_REG 0x262015C
+
+/* Workaround for PCIe boot mode support for C6678/C6670 */
+/* This is a temporary workaround should be removed once fixed in RBL */
+
+/* PCIe Config register base on C6678/C6670 */
+#define PCIE_BASE_ADDR 0x21800000
+
+/* PCIe Application registers */
+#define PCIE_APP_CMD_STATUS 0x4
+#define PCIE_OB_SIZE 0x30
+#define PCIE_APP_SERDES_CFG0 0x390
+#define PCIE_APP_SERDES_CFG1 0x394
+
+/* PCIe Local Configuration registers */
+#define PCIE_VENDER_DEVICE_ID 0x1000
+#define PCIE_STATUS_CMD 0x1004
+#define PCIE_CLASSCODE_REVID 0x1008
+#define PCIE_BAR0 0x1010
+#define PCIE_BAR1 0x1014
+#define PCIE_BAR2 0x1018
+#define PCIE_BAR3 0x101c
+#define PCIE_DEVICE_CAP 0x1074
+#define PCIE_DEV_STAT_CTRL 0x1078
+#define PCIE_LINK_STAT_CTRL 0x1080
+#define PCIE_ACCR 0x1118
+#define PCIE_DEBUG0 0x1728
+#define PCIE_PL_GEN2 0x180C
+
+/* SERDES Configuration registers */
+#define PCIE_SERDES_CFG_PLL 0x2620358
+
+#define MAGIC_ADDR (*(volatile unsigned int *)0x87fffc)
+
+/* */
+
+extern cregister volatile unsigned int IER;
+
+void waitForBoot(void)
+{
+ void (*escape)();
+ UINT32 i;
+
+ /* Disable interrupts */
+ IER = 1;
+ MAGIC_ADDR = 0;
+
+ do {
+ for (i=0; i < 100; i++)
+ asm(" nop");
+ } while (MAGIC_ADDR == 0);
+
+ escape = (void (*)())(MAGIC_ADDR);
+ (*escape)();
+}
+
+void iblPCIeWorkaround()
+{
+ UINT32 cmd_stat;
+ UINT32 reg,i;
+
+ /* Power up PCIe */
+ devicePowerPeriph (TARGET_PWR_PCIE);
+ for(i=0; i<1000; i++) asm (" NOP");
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG0), 0x00062320); /* ss clock */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG1), 0x00022320); /* ss clock */
+
+ /* Wait for PCIe PLL lock */
+ while(!(DEVICE_REG32_R(PCIE_STS_REG) & 1));
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_CLASSCODE_REVID), 0x04800001); /* class = 4 */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_LINK_STAT_CTRL), 0x10110080); /* extended synch */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_VENDER_DEVICE_ID), 0x8888104c);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEVICE_CAP), 0x288701);
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_OB_SIZE), 0x00000003); /* OB_SIZE = 8M */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_PL_GEN2), 0x0000000F);
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0020); /* Set dbi_cs2 to allow access to the BAR registers */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00003FFF);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x0007FFFF);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x003FFFFF);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x00FFFFFF);
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0); /* dbi_cs2=0 */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_STATUS_CMD), 0x00100146);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEV_STAT_CTRL), 0x0000281F);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_ACCR), 0x000001E0);
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0);
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0000007); /* enable LTSSM, IN, OB */
+ while((DEVICE_REG32_R(PCIE_BASE_ADDR + PCIE_DEBUG0) & 0x11)!=0x11); /* Wait for training to complete */
+
+ /* Wait for the Boot from Host */
+ waitForBoot();
+
+ /* Will never reach here */
+ return;
+}
+
+#endif
+
#define FPGA_BM_GPI_STATUS_LO_REG 4 /* Boot Mode GPI Status (07-00 Low Byte) Register */
#define FPGA_BM_GPI_STATUS_HI_REG 5 /* Boot Mode GPI Status (15-08 High Byte) Register */
+#define FPGA_ICS557_SEL_CTRL_REG 0x50 /* ICS 557 Clock Selection
+ Control Register*/
#define FPGA_READ_REG_CMD(x) ((x | 0x80) << 8)
+#define FPGA_WRITE_REG_CMD(addr,byte) (((addr & 0x7f) << 8) | (byte & 0xff))
+
/**
* @brief
* Enter the ROM boot loader if the FPGA boot register
*/
void iblEnterRom ()
{
- uint32 reg = DEVICE_REG32_R (DEVICE_REG_DEVSTAT);
uint32 v, dev_stat, bm_lo, bm_hi;
void (*exit)();
DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR1, 0x01000003);
/* Read the BM status lo register */
- DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_LO_REG));
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_LO_REG));
chipDelay32(10000);
v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
if ( v & 0x100)
}
/* Read the BM status hi register */
- DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_HI_REG));
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_HI_REG));
chipDelay32(10000);
v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
if ( v & 0x100)
return;
}
- /* Reset SPI */
- DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
if ( (BOOT_READ_BITFIELD(bm_lo,3,1) != 0x5) ||
(BOOT_READ_BITFIELD(bm_hi,3,3) == 0x0) )
/* Update the DEVSTAT register for the intended Boot Device and i2c Addr */
DEVICE_REG32_W (DEVICE_REG_DEVSTAT, dev_stat);
+#ifdef IBL_ENABLE_PCIE_WORKAROUND
+#define BOOT_DEVICE_MASK 0xE
+#define DEVSTAT_BOOTDEVICE_SHIFT 1
+#define PCI_BOOT_MODE 0x4
+
+ if (((dev_stat & BOOT_DEVICE_MASK)>>DEVSTAT_BOOTDEVICE_SHIFT) == PCI_BOOT_MODE) {
+ /* Write ICS 557 Clock Selection Control Register in the FPGA */
+ /* 1 : FPGA_ICS557_SEL s driven high */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0,
+ FPGA_WRITE_REG_CMD(FPGA_ICS557_SEL_CTRL_REG,1));
+ chipDelay32(10000);
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
+ iblPCIeWorkaround();
+ /* Will never reach here */
+ }
+#endif
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
(*exit)();
}
/* Update the DEVSTAT register for the actual boot configuration */
DEVICE_REG32_W (DEVICE_REG_DEVSTAT, ((bm_hi << 8) | bm_lo));
}
+
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
}
#if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
}
}
-
-
-
#endif
+
index 403cfe86103506576a6c6c6833dea1d453f71f84..853a4a073373d1063f2f59235036d9952af03f60 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
*/
#define TARGET_PWR_GPIO -1
+/**
+ * @brief
+ * The LPSC number for PCIe. PCIe is 10 for C6678/C6770
+ */
+#define TARGET_PWR_PCIE 10
+
/**
* @brief
* Flag to indicate timer 0 power up requested. The time is always on in the 6472
#define deviceConfigureForNor() 0
+/****************************************************************
+ *
+ * NOTE: Following build flags enable DEVICE specific workarounds
+ * and have code which is specific to C6670/C6678 LC EVMs
+ *
+ ****************************************************************/
+
/**
* @brief
* Support for PLL workaround to re-enter ROM boot loader.
*/
#define IBL_ENABLE_EDC 1
+/**
+ * @brief
+ * Support for enabling PCIe workarond for C6678/C6670.
+ */
+#define IBL_ENABLE_PCIE_WORKAROUND 1
+
#endif /* _TARGET_H */
+
diff --git a/src/driver/nand/nand.c b/src/driver/nand/nand.c
index 19a2399f3efc785ab800bc45834c2c0764e019da..2edf19542ab0a3bb1bade26a58622975acc619e1 100644 (file)
--- a/src/driver/nand/nand.c
+++ b/src/driver/nand/nand.c
/* Construct the logical to physical block array */
- for (i = j = startBlock; i < nandmcb.devInfo.totalBlocks; i++) {
+ for (i = startBlock, j = 0; i < nandmcb.devInfo.totalBlocks; i++) {
if (nandmcb.blocks[i] != 0xff)
nandmcb.logicalToPhysMap[j++] = i;
}
/* Construct the physical to logical block array */
- for (i = j = startBlock; i < nandmcb.devInfo.totalBlocks; i++) {
+ for (i = startBlock, j = 0; i < nandmcb.devInfo.totalBlocks; i++) {
if (nandmcb.blocks[i] == 0xff)
nandmcb.physToLogicalMap[i] = 0xff;
else
nandmcb.currentLogicalBlock = 0xffffffff;
nandmcb.currentPage = 0xffffffff;
- nand_seek (ibln->bootAddress[iblEndianIdx][iblImageIdx], 0);
+ nand_seek (0, 0);
return (0);
index 8f8f83f04ab24786c2a2e1f325cdb0d82d60e164..cf22cc07089c10bb68d1b2b0ddc8f4ffa7b21a25 100644 (file)
{
param_index = 0
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 1
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 2
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 3
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 4
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 5
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 6
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
{
param_index = 7
boot_mode = 40
- sw_pll_prediv = 1
- sw_pll_mult = 16
- sw_pll_postdiv = 2
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
options = 1
core_freq_mhz = 100
diff --git a/src/make/setupenv.bat b/src/make/setupenv.bat
--- a/src/make/setupenv.bat
+++ /dev/null
@@ -1,39 +0,0 @@
-@REM ******************************************************************************
-@REM * FILE PURPOSE: Environment Setup for building Bootloader
-@REM ******************************************************************************
-@REM * FILE NAME: setupenv.bat
-@REM *
-@REM * DESCRIPTION:
-@REM * Configures and sets up the Build Environment for Bootloader in DOS environment.
-@REM *
-@REM * Customers are expected to modify this file as per their build environment.
-@REM *
-@REM * USAGE:
-@REM * setupenv.bat
-@REM *
-@REM * Copyright (C) 2010, Texas Instruments, Inc.
-@REM *****************************************************************************
-
-@echo off
-
-REM Setup the ibl build environment if using cygwin for build
-
-REM Modify following lines based on target environment for the toolset installed
-REM Dependency is related to path for Cygwin and CGEN installed
-
-REM Specify the path to cygwin binaries and the code gen tools
-REM If the path has directory names with spaces use the below format to specify
-REM for e.g PATH=G:\cygwin\bin;C:\PROGRA~1\TEXASI~1\C6000C~1.12\bin
-set PATH=G:\cygwin\bin;t:\c6xx\cgen6_1_12\c6000\cgtools\bin
-
-REM Specify the base directory of the c6000 compiler with UNIX style path separator
-set TOOLSC6X=t:/c6xx/cgen6_1_12/c6000/cgtools
-
-REM Specify the base directory of the c6000 compiler with DOS style path separator
-set TOOLSC6XDOS=t:\c6xx\cgen6_1_12\c6000\cgtools
-
-REM # Don't modify the below variables. They are derived from the above definitions
-set PATH=%PATH%;%SystemRoot%\system32;%SystemRoot%;
-set BISONSKEL=yacc.c
-
-