C66x: Update gel file with DDR PLL values

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/src/util/i2cConfig/i2cConfig.gel b/src/util/i2cConfig/i2cConfig.gel
index 392dd31bfca533b5ade1fc97931954a6bace35b8..ef702969c503fff0123b155f8e411fd07eb1b4b8 100755 (executable)
--- a/src/util/i2cConfig/i2cConfig.gel
+++ b/src/util/i2cConfig/i2cConfig.gel
@@ -781,11 +781,11 @@ hotmenu setConfig_c6678_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */

-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0; 
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;

-       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 20;

        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;

-       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;

 
     /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
 
     /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;


@@ -995,12 +995,12 @@ hotmenu setConfig_c6670_main()
        ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 

-       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0;
+       /* DDR PLL */
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1;

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;

-       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 20;

        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;

-       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;

 
     /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
 
     /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;