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raw | patch | inline | side by side (parent: 33940e4)
raw | patch | inline | side by side (parent: 33940e4)
author | Aravind Batni <aravindbr@ti.com> | |
Wed, 9 May 2012 18:37:00 +0000 (14:37 -0400) | ||
committer | Aravind Batni <aravindbr@ti.com> | |
Wed, 9 May 2012 18:37:00 +0000 (14:37 -0400) |
src/hw/plls/pll014phi/cfgpll.c | [changed mode: 0644->0755] | patch | blob | history |
/* Set bit 14 in register 1 to disable the PLL (assert reset) */
regb = BOOT_SET_BITFIELD(regb, 1, 14, 14);
+ /* set bit 13 in register 1 for selecting the output of PASS PLL as the input to PASS */
+ regb = BOOT_SET_BITFIELD(regb, 1, 13, 13);
DEVICE_REG32_W (base + 4, regb);
reg = BOOT_SET_BITFIELD (reg, prediv - 1, 5, 0);