Changed the DDR rate to 1333 and fixed the HUA boot from NOR problem DEV.BIOS.MCSDK.02.00.00.07.Eng2
authorHao Zhang <hzhang@ti.com>
Thu, 21 Apr 2011 22:06:47 +0000 (18:06 -0400)
committerHao Zhang <hzhang@ti.com>
Thu, 21 Apr 2011 22:06:47 +0000 (18:06 -0400)
src/hw/ddrs/emif4/emif4.c
src/hw/spi/spi.c
src/hw/spi/spi_api.h
src/hw/spi/spi_loc.h
src/ibl.h
src/interp/elf/dlw_client.c
src/main/iblmain.c
src/util/i2cConfig/i2cConfig.gel

index 39c1904fd8f323558237a550ec78faa5db1596c2..ba0a63cc7ce2c9593475b480c8e2e149fcd20594 100644 (file)
@@ -33,6 +33,7 @@
 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
+#define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
 
 #define DATA0_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262043C))
 #define DATA1_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620440))
 #define DATA7_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620458))
 #define DATA8_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262045C))
 
+#define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
+#define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
+#define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
+#define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
+#define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
+#define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
+#define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
+#define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
+#define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
+
 #define RDWR_INIT_RATIO_0      (*(volatile unsigned int*)(0x0262040C))
 #define RDWR_INIT_RATIO_1      (*(volatile unsigned int*)(0x02620410))
 #define RDWR_INIT_RATIO_2      (*(volatile unsigned int*)(0x02620414))
@@ -54,6 +65,7 @@
 #define RDWR_INIT_RATIO_7      (*(volatile unsigned int*)(0x02620428))
 #define RDWR_INIT_RATIO_8      (*(volatile unsigned int*)(0x0262042C))
 
+
 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
 #define WR_DATA_SLAVE_RATIO 0xE9
 #define FIFO_WE_SLAVE_RATIO 0x106
 
+
+static void ddr3_wait (uint32 del)
+{
+    volatile unsigned int i;
+
+    for (i = 0; i < del; i++);
+
+}
+
 /*************************************************************************************************
  * FUNCTION PUROPSE: Initial EMIF4 setup
  *************************************************************************************************
 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
 {
     UINT32 v, i;
-
-#if 0
-    /* If the config registers or refresh control registers are being written
-     * disable the initialization sequence until they are all setup */
-    if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
-
-        v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
-        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-    }
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
-
-    /* Allow the configuration to occur */
-    v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
-    EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
-    DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
-
-    if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
-        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
-
-    v = cfg->sdRamRefreshCtl;
-    EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
-    DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
-#endif
-
+    
     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
-
-    /*KICK0 = 0x83E70B13;
-    KICK1 = 0x95A4F1E0;*/
-
+    
     if (v == DEVICE_C6618_JTAG_ID_VAL)
     {
+#if 0
+        /* C6678 Old 1066 configuration */
         DDR3PLLCTL0 = 0x100807C1;
         
         DDR_SDTIM1   = 0x0CCF369B;
@@ -225,9 +156,137 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
         DDR_SDTIM1; //Read MMR to ensure full leveling is complete
         
         DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
+#endif
+#if 1
+        /* C6678 1333 MHz data rate */
+        /***************** 2.2 DDR3 PLL Configuration ************/
+        DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
+        DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
+        DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ
+        ddr3_wait(1000);               //Wait for reset to complete
+        DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
+        ddr3_wait(1000);              //Wait for PLL lock
+        
+        /***************** 2.3 Basic Controller and DRAM configuration ************/
+        DDR_SDRFC    = 0x80005162;    // inhibit configuration 
+        
+        DDR_SDTIM1   = 0x1113783C;
+        DDR_SDTIM2   = 0x304F7FE3;
+        DDR_SDTIM3   = 0x559F849F;
+        
+        DDR_DDRPHYC  = 0x0010010F;
+        
+        DDR_ZQCFG    = 0x70073214;
+        
+        DDR_PMCTL    = 0x0;
+        
+        DDR_SDRFC    = 0x00005162;    // enable configuration
+        DDR_SDCFG    = 0x63222A32;    // last config write \96 DRAM init occurs
+        
+        ddr3_wait(1000);            //Wait for HW init to complete
+        DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
+        
+        /**************** 3.0 Leveling Register Configuration ********************/
+        /* Using partial automatic leveling due to errata */
+        
+        /**************** 3.2 Invert Clock Out ********************/
+        DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
+        DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
+        DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
+        DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
+        
+        
+        /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+        DATA0_WRLVL_INIT_RATIO = 0x20;
+        DATA1_WRLVL_INIT_RATIO = 0x24;
+        DATA2_WRLVL_INIT_RATIO = 0x3A;
+        DATA3_WRLVL_INIT_RATIO = 0x38;
+        DATA4_WRLVL_INIT_RATIO = 0x51;
+        DATA5_WRLVL_INIT_RATIO = 0x5E;
+        DATA6_WRLVL_INIT_RATIO = 0x5E;
+        DATA7_WRLVL_INIT_RATIO = 0x5E;
+        DATA8_WRLVL_INIT_RATIO = 0x44;
+        
+        DATA0_GTLVL_INIT_RATIO = 0xA1;
+        DATA1_GTLVL_INIT_RATIO = 0x9E;
+        DATA2_GTLVL_INIT_RATIO = 0xA7;
+        DATA3_GTLVL_INIT_RATIO = 0xA9;
+        DATA4_GTLVL_INIT_RATIO = 0xCA;
+        DATA5_GTLVL_INIT_RATIO = 0xBE;
+        DATA6_GTLVL_INIT_RATIO = 0xDD;
+        DATA7_GTLVL_INIT_RATIO = 0xDD;
+        DATA8_GTLVL_INIT_RATIO = 0xBA;
+        
+        DDR3_CONFIG_REG_23 |= 0x00000200;
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
+        DDR_RDWR_LVL_CTRL = 0x80000000;
+#endif
+        
+#if 0
+        /* C6678 New 1066 rate */
+        /***************** 2.2 DDR3 PLL Configuration ************/
+        DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
+        DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
+        DDR3PLLCTL0 = 0x0F0807C1;       //Configure CLKR, CLKF, CLKOD, BWADJ
+        ddr3_wait(1000);              //Wait for reset to complete
+        DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
+        ddr3_wait(1000);
+        
+        /***************** 2.3 Basic Controller and DRAM configuration ************/
+        DDR_SDRFC    = 0x8000411B;    // inhibit configuration 
+        DDR_SDTIM1   = 0x0CCF36B3;
+        DDR_SDTIM2   = 0x303F7FDA;
+        DDR_SDTIM3   = 0x559F83AF;
+        
+        DDR_DDRPHYC  = 0x0010010A;
+        DDR_ZQCFG    = 0x70073214;
+        
+        //DDR_PMCTL    = 0x0;
+        DDR_SDRFC    = 0x0000411B;    // enable configuration
+        DDR_SDCFG    = 0x63211A32;    // last config write \96 DRAM init occurs
+        
+        ddr3_wait(1000);             //Wait for HW init to complete
+        
+        DDR_SDRFC = 0x00001040;       //Refresh rate = (7.8*666MHz]
+        
+        /**************** 3.0 Leveling Register Configuration ********************/
+        /* Using partial automatic leveling due to errata */
+        
+        /**************** 3.2 Invert Clock Out ********************/
+        DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
+        DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
+        DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
+        DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
+        
+        /**************** 3.3+3.4 Partial Automatic Leveling ********************/
+        DATA0_WRLVL_INIT_RATIO = 0x19;//0x4C;
+        DATA1_WRLVL_INIT_RATIO = 0x1C;//0x4C;
+        DATA2_WRLVL_INIT_RATIO = 0x2F;//0x4C;
+        DATA3_WRLVL_INIT_RATIO = 0x2D;//0x42;
+        DATA4_WRLVL_INIT_RATIO = 0x42;//0x2D;
+        DATA5_WRLVL_INIT_RATIO = 0x4C;//0x2F;
+        DATA6_WRLVL_INIT_RATIO = 0x4C;//0x1C;
+        DATA7_WRLVL_INIT_RATIO = 0x4C;//0x19;
+        DATA8_WRLVL_INIT_RATIO = 0x37;
+        
+        DATA0_GTLVL_INIT_RATIO = 0x8D;//0xBC;
+        DATA1_GTLVL_INIT_RATIO = 0x8A;//0xBC;
+        DATA2_GTLVL_INIT_RATIO = 0x91;//0xA4;
+        DATA3_GTLVL_INIT_RATIO = 0x93;//0xAE;
+        DATA4_GTLVL_INIT_RATIO = 0xAE;//0x93;
+        DATA5_GTLVL_INIT_RATIO = 0xA4;//0x91;
+        DATA6_GTLVL_INIT_RATIO = 0xBC;//0x8A;
+        DATA7_GTLVL_INIT_RATIO = 0xBC;//0x8D;
+        DATA8_GTLVL_INIT_RATIO = 0xA1;
+        
+        DDR3_CONFIG_REG_23 |= 0x00000200;
+        DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
+        DDR_RDWR_LVL_CTRL = 0x80000000;
+#endif
     }
-    else
+    else if (v == DEVICE_C6616_JTAG_ID_VAL)
     {
+        /* C6670 800 M rate */
         DDR3PLLCTL1 |= 0x00000040;    //Set ENSAT = 1
         DDR3PLLCTL1 |= 0x00002000;    //Set RESET bit before programming DDR3PLLCTL0
         DDR3PLLCTL0 = 0x02000140;
@@ -259,7 +318,97 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
         
         DDR_SDRFC    = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
     }
-
+    else
+    {
+        /* C64x configuration */
+        /* If the config registers or refresh control registers are being written
+         * disable the initialization sequence until they are all setup */
+        if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
+            
+            v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+            EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+        }
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
+        
+        /* Allow the configuration to occur */
+        v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
+        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
+        
+        if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
+            DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
+        
+        v = cfg->sdRamRefreshCtl;
+        EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
+        DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+    }
+    
     return (0);
 
 } /* hwEmif4p0Enable */
index d9a351425ac37f8c736ac0a6b6e0d6d1730009e4..6702858191204917a2eec672ddd5d26e4e7c56cb 100644 (file)
@@ -114,7 +114,7 @@ SINT16 hwSpiConfig (spiConfig_t *cfg)
  *************************************************************************************************
  * DESCRIPTION: A bi-directional transfer is done
  *************************************************************************************************/
-SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate)
+SINT16 hw_spi_xfer (UINT32 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate)
 {
     UINT32 v;
     UINT32 i;
@@ -227,7 +227,7 @@ SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *c
  *************************************************************************************************
  * DESCRIPTION: A single data block of a fixed size is read
  *************************************************************************************************/
-SINT16 hwSpiRead (UINT32 addr, UINT16 sizeBytes, UINT8 *data)
+SINT16 hwSpiRead (UINT32 addr, UINT32 sizeBytes, UINT8 *data)
 {
     UINT32 n;
     UINT8  command[4];
index 247931bb435818a4e2911231b5e09867bfb2700e..abf82bec4276b150e22fcf788c9102864ed4b5c5 100644 (file)
@@ -20,7 +20,7 @@ typedef struct spiConfig_s  {
 } spiConfig_t;
 
 SINT16 hwSpiConfig (spiConfig_t *spiCfg);
-SINT16 hwSpiRead (UINT32 addr, UINT16 sizeBytes, UINT8 *data);
+SINT16 hwSpiRead (UINT32 addr, UINT32 sizeBytes, UINT8 *data);
 void hwSpiEnableXfer (UINT32 port);
 void hwSpiDisableXfer (UINT32 port);
 
index 679dd21cfd71dabc88e5fa50d1d28ab1bb25e1a0..8222260e146eade8006bdb50b4df97deb3d97cd3 100644 (file)
@@ -57,6 +57,6 @@
 #define SPI_COMMAND_WRITE_ENABLE    0x06
 #define SPI_COMMAND_ERASE_SECTOR    0x20
 
-SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate);
+SINT16 hw_spi_xfer (UINT32 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate);
 
 #endif /* _SPI_LOC_H */
index e576be0c0ead256b269a2be9d5cbee9ebc7a74ec..6ee3d10e148fa218fe769079ff596bee8e5b1a22 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
@@ -65,9 +65,9 @@
 
 /**
  * @brief
- *  The version number, 1.0.0.2
+ *  The version number, 1.0.0.3
  */
-#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,2)
+#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,3)
 
 
 /**
index 2bf2103a4dd9e366a1ee09246445f98d00734e66..d9c00d332fdc5e0a75d01228a3f704fb373913c6 100644 (file)
@@ -159,9 +159,14 @@ BOOL DLIF_allocate(struct DLOAD_MEMORY_REQUEST *targ_req)
    /*   load placement or both load and run placement, then we can do the    */
    /*   copy.                                                                */
    /*------------------------------------------------------------------------*/
-   memset(targ_req->host_address, 0, obj_desc->memsz_in_bytes);
-   fseek(f,targ_req->offset,SEEK_SET);
-   fread(targ_req->host_address,obj_desc->objsz_in_bytes,1,f);
+   if (obj_desc->objsz_in_bytes)
+   {
+       /* Do not clear uninitialized data section, so that the section can 
+          be mapped to the same region IBL uses */ 
+       memset(targ_req->host_address, 0, obj_desc->memsz_in_bytes);
+       fseek(f,targ_req->offset,SEEK_SET);
+       fread(targ_req->host_address,obj_desc->objsz_in_bytes,1,f);
+   }
 
    /*------------------------------------------------------------------------*/
    /* Once we have target address for this allocation, add debug information */
index 3bcac31e9f124cebcf0983467529e146f858db7b..fa0b61b9d6336e5415c0781f28a4e19ff4bd412c 100644 (file)
@@ -66,6 +66,8 @@
 #include "ibl_elf.h"
 #include <string.h>
 
+extern cregister unsigned int IER;
+
 /**
  *  @brief
  *      Data structures shared between the 1st and 2nd stage IBL load
@@ -231,6 +233,7 @@ void iblPmemCfg (int32 interface, int32 port, bool enableNand)
 void main (void)
 {
     int32 i, j;
+    UINT32 v;
 
     /* Initialize the status structure */
     iblMemset (&iblStatus, 0, sizeof(iblStatus_t));
@@ -261,6 +264,15 @@ void main (void)
 
     /* Try booting forever */
     for (;;)  {
+        v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
+        if (
+            (v == DEVICE_C6618_JTAG_ID_VAL)         || 
+            (v == DEVICE_C6616_JTAG_ID_VAL)
+           )
+        {
+            /* Disable interrupts, HUA does not work if IER is not cleared */
+            IER = 0;
+        }
 
         /* Start looping through the boot modes to find the one with the highest priority
          * value, and try to boot it. */
index fba6a7d8ecfa243fab5d688f1e1ff66280640e4b..3f33d1e3a38b43761206c1119ecf6fc554aaf1c1 100755 (executable)
@@ -596,7 +596,7 @@ hotmenu setConfig_c6678_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;