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raw | patch | inline | side by side (parent: 012a652)
raw | patch | inline | side by side (parent: 012a652)
author | Sandeep Nair <a0875039@gt48xvq51.gt.design.ti.com> | |
Thu, 10 Mar 2011 02:50:11 +0000 (21:50 -0500) | ||
committer | Sandeep Nair <a0875039@gt48xvq51.gt.design.ti.com> | |
Thu, 10 Mar 2011 02:50:11 +0000 (21:50 -0500) |
release.sh | patch | blob | history | |
src/make/Makefile | patch | blob | history | |
src/util/i2cConfig/i2cConfig.gel | patch | blob | history |
diff --git a/release.sh b/release.sh
index dafa12c7b56da332cfe8baf1c8aa89423d78c655..f67f6bc5d905274b5144e80ced29b61d941635b4 100755 (executable)
--- a/release.sh
+++ b/release.sh
#!/bin/sh
# Generate the source release tarballs
-export IBL_VERSION="1_0_1"
+export IBL_VERSION="1_0_0_1"
cd ../
if [ -f ibl_src_$IBL_VERSION.tar ]; then rm ibl_src_$IBL_VERSION.tar; fi
diff --git a/src/make/Makefile b/src/make/Makefile
index 0aff8d633fe09e94171324651c3704671fbf24bc..3c182afa38a743ea9c361e6b1ca397a09af42c12 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
make -C ../util/romparse clean
make -C ../test/test1 clean
make -C ../test/test2 clean
+ find ../ -name *.oc | xargs rm -f
+ find ../ -name *.dc | xargs rm -f
index ea807554785d7230910aa80c9abee87b347d6189..19193d969b262edfd309bdf2d8938fe43ce0fe61 100755 (executable)
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,21);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Leave the hardware address as 0 so the e-fuse value will be used */
-
-
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
- ibl.ethConfig[0].ethInfo.fileName[1] = '6';
- ibl.ethConfig[0].ethInfo.fileName[2] = '4';
- ibl.ethConfig[0].ethInfo.fileName[3] = '7';
- ibl.ethConfig[0].ethInfo.fileName[4] = '2';
- ibl.ethConfig[0].ethInfo.fileName[5] = '-';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[8] = '.';
- ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
- ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* For port 1 use bootp */
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;
- ibl.ethConfig[1].port = 1;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[1].doBootp = TRUE;
- ibl.ethConfig[1].useBootpServerIp = TRUE;
- ibl.ethConfig[1].useBootpFileName = TRUE;
- ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
/* SGMII not present */
- ibl.sgmiiConfig[0].adviseAbility = 0;
- ibl.sgmiiConfig[0].control = 0;
- ibl.sgmiiConfig[0].txConfig = 0;
- ibl.sgmiiConfig[0].rxConfig = 0;
- ibl.sgmiiConfig[0].auxConfig = 0;
-
- ibl.sgmiiConfig[1].adviseAbility = 0;
- ibl.sgmiiConfig[1].control = 0;
- ibl.sgmiiConfig[1].txConfig = 0;
- ibl.sgmiiConfig[1].rxConfig = 0;
- ibl.sgmiiConfig[1].auxConfig = 0;
-
-
- /* Leave the hardware address as 0 so the e-fuse value will be used */
- ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
-
-
- /* Leave all remaining fields as 0 since bootp will fill them in */
-
-
- /* Even though the entire range of DDR2 is chosen, the load will */
- /* stop when the ftp reaches the end of the file */
-
- ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
-
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 8;
ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
+ /* spiConfig and emifConfig not needed */
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
-
- ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_AUTO;
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
- ibl.nandConfig.nandInfo.busWidthBits = 8;
- ibl.nandConfig.nandInfo.pageSizeBytes = 2048;
- ibl.nandConfig.nandInfo.pageEccBytes = 64;
- ibl.nandConfig.nandInfo.pagesPerBlock = 64;
- ibl.nandConfig.nandInfo.totalBlocks = 1024;
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- ibl.nandConfig.nandInfo.addressBytes = 4;
- ibl.nandConfig.nandInfo.lsbFirst = TRUE;
- ibl.nandConfig.nandInfo.blockOffset = 22;
- ibl.nandConfig.nandInfo.pageOffset = 16;
- ibl.nandConfig.nandInfo.columnOffset = 0;
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- ibl.nandConfig.nandInfo.resetCommand = 0xff;
- ibl.nandConfig.nandInfo.readCommandPre = 0;
- ibl.nandConfig.nandInfo.readCommandPost = 0x30;
- ibl.nandConfig.nandInfo.postCommand = TRUE;
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,103,200);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,103,58);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,103,1);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+ /* Leave the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '2';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
}
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Set the hardware address as 0 so the e-fuse value will be used */
- ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
- ibl.ethConfig[0].ethInfo.fileName[1] = '6';
- ibl.ethConfig[0].ethInfo.fileName[2] = '4';
- ibl.ethConfig[0].ethInfo.fileName[3] = '7';
- ibl.ethConfig[0].ethInfo.fileName[4] = '4';
- ibl.ethConfig[0].ethInfo.fileName[5] = '-';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[8] = '.';
- ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
- ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
-
- /* There is no port 1 on the 6474 */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
- /* SGMII is present */
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
ibl.sgmiiConfig[0].rxConfig = 0x00081023;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+ /* There is no port 1 on the 6474 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 8;
ibl.mdioConfig.mdioClkDiv = 0x26;
ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
- ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
- ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
- ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (13 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
- ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (13 << 16) | 0x8140;
ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 10,218,109,35);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 10,218,109,196);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 10,218,109,1);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.chkSum = 0;
}
menuitem "EVM c6474 Lite EVM IBL";
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Set the hardware address as 0 so the e-fuse value will be used */
- ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
- ibl.ethConfig[0].ethInfo.fileName[1] = '6';
- ibl.ethConfig[0].ethInfo.fileName[2] = '4';
- ibl.ethConfig[0].ethInfo.fileName[3] = '7';
- ibl.ethConfig[0].ethInfo.fileName[4] = '4';
- ibl.ethConfig[0].ethInfo.fileName[5] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[6] = '-';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[8] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[9] = '.';
- ibl.ethConfig[0].ethInfo.fileName[10] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[11] = 'i';
- ibl.ethConfig[0].ethInfo.fileName[12] = 'n';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
-
- /* There is no port 1 on the 6474 Lite EVM */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
- /* SGMII is present */
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000e23;
ibl.sgmiiConfig[0].rxConfig = 0x00081023;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+ /* There is no port 1 on the 6474 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 5;
ibl.mdioConfig.mdioClkDiv = 0x20;
ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,114);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
- /* This board has NAND. We will enable later */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.chkSum = 0;
}
menuitem "EVM c6457 EVM IBL";
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,115);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Set the hardware address as 0 so the e-fuse value will be used */
- ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
- ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
- ibl.ethConfig[0].ethInfo.fileName[1] = '6';
- ibl.ethConfig[0].ethInfo.fileName[2] = '4';
- ibl.ethConfig[0].ethInfo.fileName[3] = '5';
- ibl.ethConfig[0].ethInfo.fileName[4] = '7';
- ibl.ethConfig[0].ethInfo.fileName[5] = '-';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[8] = '.';
- ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
- ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* There is no port 1 on the 6457 Lite EVM */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
- /* SGMII is present */
+ /* SGMII 0 is present */
+ ibl.sgmiiConfig[0].configure = TRUE;
ibl.sgmiiConfig[0].adviseAbility = 0x9801;
ibl.sgmiiConfig[0].control = 0x20;
ibl.sgmiiConfig[0].txConfig = 0x00000e21;
ibl.sgmiiConfig[0].rxConfig = 0x00081021;
ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+ /* There is no port 1 on the 6457 */
+ ibl.sgmiiConfig[1].configure = FALSE;
+
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 5;
ibl.mdioConfig.mdioClkDiv = 0xa5;
ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
- /* This board has NAND. We will enable later */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,115);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '7';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
}
menuitem "EVM c6455 IBL";
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* There is no e-fuse mac address. A value must be assigned */
- ibl.ethConfig[0].ethInfo.hwAddress[0] = 10;
- ibl.ethConfig[0].ethInfo.hwAddress[1] = 224;
- ibl.ethConfig[0].ethInfo.hwAddress[2] = 166;
- ibl.ethConfig[0].ethInfo.hwAddress[3] = 102;
- ibl.ethConfig[0].ethInfo.hwAddress[4] = 87;
- ibl.ethConfig[0].ethInfo.hwAddress[5] = 25;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
- ibl.ethConfig[0].ethInfo.fileName[1] = '6';
- ibl.ethConfig[0].ethInfo.fileName[2] = '4';
- ibl.ethConfig[0].ethInfo.fileName[3] = '5';
- ibl.ethConfig[0].ethInfo.fileName[4] = '5';
- ibl.ethConfig[0].ethInfo.fileName[5] = '-';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[8] = '.';
- ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
- ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* There is no ethernet port 1 */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
-
/* SGMII not present */
- ibl.sgmiiConfig[0].adviseAbility = 0;
- ibl.sgmiiConfig[0].control = 0;
- ibl.sgmiiConfig[0].txConfig = 0;
- ibl.sgmiiConfig[0].rxConfig = 0;
- ibl.sgmiiConfig[0].auxConfig = 0;
-
- ibl.sgmiiConfig[1].adviseAbility = 0;
- ibl.sgmiiConfig[1].control = 0;
- ibl.sgmiiConfig[1].txConfig = 0;
- ibl.sgmiiConfig[1].rxConfig = 0;
- ibl.sgmiiConfig[1].auxConfig = 0;
-
-
+ ibl.sgmiiConfig[0].configure = FALSE;
+ ibl.sgmiiConfig[1].configure = FALSE;
/* MDIO configuration */
ibl.mdioConfig.nMdioOps = 0;
ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
+ /* spiConfig and emifConfig not needed */
+
+ /* Ethernet configuration for Boot mode 0 */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,118);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* There is no e-fuse mac address. A value must be assigned */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 10;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 224;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 166;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 102;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 87;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 25;
+
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '5';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+ /* Alternative bootMode not configured for now */
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+ ibl.chkSum = 0;
}