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raw | patch | inline | side by side (parent: 389a671)
raw | patch | inline | side by side (parent: 389a671)
author | Sandeep Paulraj <s-paulraj@ti.com> | |
Mon, 20 Jun 2011 21:32:00 +0000 (17:32 -0400) | ||
committer | Sandeep Paulraj <s-paulraj@ti.com> | |
Thu, 30 Jun 2011 16:04:38 +0000 (12:04 -0400) |
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
index e162d68dd458ef258251a6a1165059f17109333c..f23e6f5186792c9d65fa57b9ceb6d320cb006ec8 100644 (file)
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
-#define NAND_BYTES_PER_PAGE 2048
#define ECC_BLOCK_SIZE 256
#define ECC_BLOCK_SIZE 256
-#define NAND_SPARE_BYTES_PER_PAGE 64
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
index 0e1b03066a07e10e11880b64183a7fa5d147d44c..5296f3f24ccb4a6d83ef3bad901b06e610d9264c 100644 (file)
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
-#define NAND_BYTES_PER_PAGE 2048
#define ECC_BLOCK_SIZE 256
#define ECC_BLOCK_SIZE 256
-#define NAND_SPARE_BYTES_PER_PAGE 64
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
index 67e557ad6c9345cf590c6ca1298e1a0622577758..019c47ed938b8814935c0d0c63b129179e2475dd 100644 (file)
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
-#define NAND_BYTES_PER_PAGE 2048
#define ECC_BLOCK_SIZE 256
#define ECC_BLOCK_SIZE 256
-#define NAND_SPARE_BYTES_PER_PAGE 64
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
index 5b3aa636b9239af56c29b3802a027938d30a5520..b8b46687f701e06f337cd7f3a863122555c9ec23 100644 (file)
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
-#define NAND_BYTES_PER_PAGE 2048
#define ECC_BLOCK_SIZE 256
#define ECC_BLOCK_SIZE 256
-#define NAND_SPARE_BYTES_PER_PAGE 64
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
index 6498114c9099b3a2c32199db8a03954a8a5761e9..cda57677153ee2128707e3fedd1ae6701e2679de 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
#define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
#define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
-#define NAND_BYTES_PER_PAGE 512
#define ECC_BLOCK_SIZE 256
#define ECC_BLOCK_SIZE 256
-#define NAND_SPARE_BYTES_PER_PAGE 16
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \
/* NAND address pack macro */
#define PACK_ADDR(col, page, block) \