IBL-c6x: C6474 Lite device specific files

This commit adds device specific files for the
C6474 Lite EVM

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/src/cfg/c6474l/iblcfg.h b/src/cfg/c6474l/iblcfg.h
index 9582fa0e9fa6e93b374ed47ae5757e0807baec2c..cdee0dd6caebbcf4232fd2f05845d6d9380a40c9 100644 (file)
--- a/src/cfg/c6474l/iblcfg.h
+++ b/src/cfg/c6474l/iblcfg.h
@@ -1,66 +1,76 @@
-/**************************************************************************
- * FILE PURPOSE: Provide build time configurations for the IBL
- **************************************************************************
- * FILE NAME: iblcfg.h
- *
- * DESCRIPTION: Build time configuration
- *
- * @file iblcfg.h
- *
- * @brief
- *      Build time configurations for the c6474 Lite EVM ibl are defined
- *
- ***************************************************************************/
-#ifndef IBLCFG_H
-#define IBLCFG_H
-
-/**
- * @brief  The maximum number of UDP sockets in the system
- */
-#define MAX_UDP_SOCKET          3
-
-
-/**
- * @brief The maximum number of timers in the system
- */
-#define MAX_TIMER_BLOCKS        5
-
-
-/**
- * @brief The size in bytes of the internal stream buffer
- */
-#define MAX_SIZE_STREAM_BUFFER  1024
-
-
-/**
- * @brief The maximum number of functions supported for BIS mode
- */
-#define MAX_BIS_FUNCTION_SUPPORT    3
-
-
-/**
- * @brief No I/O sections accepted in boot table format
- */
-#define BOOTCONFIG_NO_BTBL_IO
-
-/**
- * @brief The I2C bus address and data address of the ibl table.
- */
-#define IBL_I2C_DEV_FREQ_MHZ            1000
-#define IBL_I2C_CLK_FREQ_KHZ            100
-#define IBL_I2C_OWN_ADDR                10
-#define IBL_I2C_CFG_ADDR_DELAY          0x100       /* Delay between sending the address and reading data */
-
-#ifndef IBL_I2C_CFG_EEPROM_BUS_ADDR
- #define IBL_I2C_CFG_EEPROM_BUS_ADDR    0x50
-#endif
-
-#define IBL_I2C_CFG_TABLE_DATA_ADDR     (0x10000 - 0x300)
- 
- 
-
-
-
-#endif
-
-
+/**************************************************************************\r
+ * FILE PURPOSE: Provide build time configurations for the IBL\r
+ **************************************************************************\r
+ * FILE NAME: iblcfg.h\r
+ *\r
+ * DESCRIPTION: Build time configuration\r
+ *\r
+ * @file iblcfg.h\r
+ *\r
+ * @brief\r
+ *      Build time configurations for the c6474 Lite ibl are defined\r
+ *\r
+ ***************************************************************************/\r
+#ifndef IBLCFG_H\r
+#define IBLCFG_H\r
+\r
+/**\r
+ * @brief  The maximum number of UDP sockets in the system\r
+ */\r
+#define MAX_UDP_SOCKET          3\r
+\r
+\r
+/**\r
+ * @brief The maximum number of timers in the system\r
+ */\r
+#define MAX_TIMER_BLOCKS        5\r
+\r
+\r
+/**\r
+ * @brief The size in bytes of the internal stream buffer\r
+ */\r
+#define MAX_SIZE_STREAM_BUFFER  1024\r
+\r
+\r
+/**\r
+ * @brief The maximum number of functions supported for BIS mode\r
+ */\r
+#define MAX_BIS_FUNCTION_SUPPORT    3\r
+\r
+\r
+/**\r
+ * @brief No I/O sections accepted in boot table format\r
+ */\r
+#define BOOTCONFIG_NO_BTBL_IO\r
+\r
+/**\r
+ * @brief The I2C bus address and data address of the ibl table.\r
+ */\r
+#define IBL_I2C_DEV_FREQ_MHZ            1000\r
+#define IBL_I2C_CLK_FREQ_KHZ            100\r
+#define IBL_I2C_OWN_ADDR                10\r
+#define IBL_I2C_CFG_ADDR_DELAY          0x100       /* Delay between sending the address and reading data */\r
+\r
+#ifndef IBL_I2C_CFG_EEPROM_BUS_ADDR\r
+ #define IBL_I2C_CFG_EEPROM_BUS_ADDR    0x50\r
+#endif\r
+\r
+#define IBL_I2C_CFG_TABLE_DATA_ADDR     (0x10000 - 0x300)\r
+ \r
+ \r
+\r
+/**\r
+ * @brief No NAND support. Define the function call to be a void statement\r
+ */\r
+#define iblNandBoot()\r
+\r
+/**\r
+ * @brief No Elf support\r
+ */\r
+#define iblIsElf(x)         FALSE\r
+#define iblBootElf(x,y)     for (;;);\r
+\r
+\r
+#endif\r
+\r
+\r

diff --git a/src/device/c6474l/c6474l.c b/src/device/c6474l/c6474l.c
new file mode 100755 (executable)
index 0000000..ca39748
--- /dev/null
+++ b/src/device/c6474l/c6474l.c
@@ -0,0 +1,163 @@
+/************************************************************************************\r
+ * FILE PURPOSE: C6474 Device Specific functions\r
+ ************************************************************************************\r
+ * FILE NAME: c6474l.c\r
+ *\r
+ * DESCRIPTION: Implements the device specific functions for the IBL\r
+ *\r
+ * @file c6474l.c\r
+ *\r
+ * @brief\r
+ *  This file implements the device specific functions for the IBL\r
+ *\r
+ ************************************************************************************/\r
+#include "ibl.h"\r
+#include "device.h"\r
+#include "pllapi.h"\r
+#include "emif31api.h"\r
+#include "pscapi.h"\r
+#include "gpio.h"\r
+#include <string.h>\r
+\r
+extern cregister unsigned int DNUM;\r
+\r
+\r
+/**\r
+ *  @brief Determine if an address is local\r
+ *\r
+ *  @details\r
+ *    Examines an input address to determine if it is a local address\r
+ */\r
+bool address_is_local (Uint32 addr)\r
+{\r
+    /* L2 */\r
+    if ((addr >= 0x00800000) && (addr < 0x00898000))\r
+        return (TRUE);\r
+\r
+    /* L1P */\r
+    if ((addr >= 0x00e00000) && (addr < 0x00e08000))\r
+        return (TRUE);\r
+\r
+    /* L2D */\r
+    if ((addr >= 0x00f00000) && (addr < 0x00f08000))\r
+        return (TRUE);\r
+\r
+    return (FALSE);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Convert a local l1d, l1p or l2 address to a global address\r
+ *\r
+ * @details\r
+ *  The global address is formed. If the address is not local then\r
+ *  the input address is returned\r
+ */\r
+Uint32 deviceLocalAddrToGlobal (Uint32 addr)\r
+{\r
+\r
+    if (address_is_local (addr))\r
+        addr = (1 << 28) | (DNUM << 24) | addr;\r
+\r
+    return (addr);\r
+\r
+}\r
+        \r
+        \r
+/**\r
+ * @brief Configure the PLLs\r
+ *\r
+ * @details\r
+ *   Only the main PLL can be configured here. The DDR pll is enabled by default,\r
+ *   and the network PLL is enabled through serdes configuration.\r
+ *   the multiplier and dividers.\r
+ */\r
+void devicePllConfig (void)\r
+{\r
+    if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)\r
+        hwPllSetPll (MAIN_PLL, \r
+                     ibl.pllConfig[ibl_MAIN_PLL].prediv,\r
+                     ibl.pllConfig[ibl_MAIN_PLL].mult,\r
+                     ibl.pllConfig[ibl_MAIN_PLL].postdiv);\r
+\r
+}\r
+\r
+/**\r
+ * @brief\r
+ *   Enable the DDR\r
+ *\r
+ * @details\r
+ *   The DDR controller on the c6474 is an emif 3.1. The controller is\r
+ *   initialized directly with the supplied values\r
+ */\r
+void deviceDdrConfig (void)\r
+{\r
+    if (ibl.ddrConfig.configDdr != 0)\r
+        hwEmif3p1Enable (&ibl.ddrConfig.uEmif.emif3p1);\r
+\r
+}\r
+        \r
+\r
+/**\r
+ *  @brief Power up a peripheral\r
+ *\r
+ *  @details\r
+ *    Boot peripherals are powered up\r
+ */\r
+int32 devicePowerPeriph (int32 modNum)\r
+{\r
+    /* If the input value is < 0 there is nothing to power up */\r
+    if (modNum < 0)\r
+        return (0);\r
+\r
+\r
+    if (modNum >= TARGET_PWR_MAX_MOD)\r
+        return (-1);\r
+\r
+    return ((int32)pscEnableModule(modNum));\r
+        \r
+}\r
+\r
+\r
+/**\r
+ *  @brief  Enable the pass through version of the nand controller\r
+ *\r
+ *  @details  On the evm the nand controller is enabled by setting \r
+ *            gpio 14 high\r
+ */\r
+#if 0\r
+int32 deviceConfigureForNand(void)\r
+{\r
+       hwGpioSetDirection(NAND_MODE_GPIO, GPIO_OUT);\r
+       hwGpioSetOutput(NAND_MODE_GPIO);\r
+    return (0);\r
+\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ *  @brief\r
+ *    The e-fuse mac address is loaded\r
+ */\r
+void deviceLoadDefaultEthAddress (uint8 *maddr)\r
+{\r
+    uint32 macA, macB;\r
+\r
+    /* Read the e-fuse mac address */\r
+    macA = *((uint32 *)0x2880834);\r
+    macB = *((uint32 *)0x2880838);\r
+\r
+    maddr[0] = (macB >>  8) & 0xff;\r
+    maddr[1] = (macB >>  0) & 0xff;\r
+    maddr[2] = (macA >> 24) & 0xff;\r
+    maddr[3] = (macA >> 16) & 0xff;\r
+    maddr[4] = (macA >>  8) & 0xff;\r
+    maddr[5] = (macA >>  0) & 0xff;\r
+}\r
+\r
+\r
+\r
+\r
+\r

diff --git a/src/device/c6474l/target.h b/src/device/c6474l/target.h
new file mode 100755 (executable)
index 0000000..855714c
--- /dev/null
+++ b/src/device/c6474l/target.h
@@ -0,0 +1,166 @@
+/**************************************************************************\r
+ * FILE PURPOSE: Target specific definitions\r
+ **************************************************************************\r
+ * FILE NAME: target.h\r
+ *\r
+ * DESCRIPTION: This file defines target specific values used by low level\r
+ *                             drivers.\r
+ *\r
+ * @file target.h\r
+ *\r
+ * @brief\r
+ *  Low level target specific values are defined\r
+ *\r
+ ***************************************************************************/\r
+ \r
+ \r
+/** \r
+ *  @brief\r
+ *   Device EMAC definitions\r
+ */\r
+#define TARGET_DEVICE_CPMAC\r
+ \r
+#define TARGET_EMAC_N_PORTS            1\r
+\r
+#define TARGET_EMAC_BASE_ADDRESSES     { 0x02c80000u }\r
+#define TARGET_EMAC_DSC_BASE_ADDR      { 0x02c82000u }\r
+\r
+#define TARGET_SGMII_BASE_ADDRESSES    { 0x02c40000u }\r
+\r
+/* SGMII offsets (at least the serdes configs, vary between devices, so\r
+ * they are defined here. */\r
+#define TARGET_SGMII_IDVER             0x000\r
+#define TARGET_SGMII_SOFT_RESET        0x004\r
+#define TARGET_SGMII_CONTROL           0x010\r
+#define TARGET_SGMII_STATUS            0x014\r
+#define TARGET_SGMII_MR_ADV_ABILITY    0x018\r
+#define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020\r
+#define TARGET_SGMII_TX_CFG            0x030\r
+#define TARGET_SGMII_RX_CFG            0x034\r
+#define TARGET_SGMII_AUX_CFG           0x038\r
+\r
+/* Leave mdio disabled */\r
+#define dev_mdio_open()     1\r
+\r
+/* No chip level reset required for ethernet, the function call is made a void statment */\r
+#define deviceSetEthResetState(x,y)\r
+\r
+/* The mac control register values */\r
+#define TARGET_MAC_CONTROL       ( 1 << 18)            /* EXT_EN              */     \\r
+                            | ( 0 << 9 )            /* Round robin         */     \\r
+                               | ( 1 << 7 )            /* GIG                 */     \\r
+                            | ( 0 << 6 )            /* TX pacing disabled  */     \\r
+                            | ( 1 << 5 )            /* GMII RX & TX        */     \\r
+                            | ( 0 << 4 )            /* TX flow disabled    */     \\r
+                            | ( 0 << 3 )            /* RX flow disabled    */     \\r
+                            | ( 0 << 1 )            /* Loopback enabled    */     \\r
+                            | ( 1 << 0 )            /* full duplex         */\r
+\r
+\r
+/**\r
+ *  @brief\r
+ *    Device Timer definitions\r
+ */\r
+#define TIMER0_BASE             0x02910000u\r
+\r
+#define TIMER_INPUT_DIVIDER     6           /* Timer driven from cpu clock / 6 */\r
+\r
+\r
+/**\r
+ *  @def MAIN_PLL\r
+ */\r
+#define MAIN_PLL        0   /**< The index to the main PLL */\r
+\r
+\r
+/**\r
+ *  @brief\r
+ *    Device PLL definitions\r
+ */\r
+#define DEVICE_PLL_BASE(x)  ((x) == MAIN_PLL ? 0x29a0000 : 0)\r
+\r
+\r
+/**\r
+ * @brief \r
+ *  Device PSC definitions\r
+ */\r
+#define DEVICE_PSC_BASE     0x02ac0000u\r
+\r
+/**\r
+ * @brief\r
+ *  The ethernet is in the always on domain */\r
+#define TARGET_PWR_ETH(x)   -1\r
+\r
+/**\r
+ *  @brief\r
+ *    The nand is done through gpio, which is always powered up.\r
+ *    A value < 0 tells the low level psc driver to simply return success\r
+ */\r
+#define TARGET_PWR_NAND     -1\r
+\r
+/**\r
+ * @brief\r
+ *  Flag to indicate timer 0 power up requested. The time is always on in the 6474\r
+ */\r
+#define TARGET_PWR_TIMER_0  -1\r
+\r
+\r
+/**\r
+ *  @brief\r
+ *    Device DDR controller definitions\r
+ */\r
+#define DEVICE_DDR_BASE  0x70000000\r
+\r
+/**\r
+ * @brief\r
+ *  The highest module number\r
+ */\r
+#define TARGET_PWR_MAX_MOD  5\r
+ \r
+\r
+/**\r
+ * @brief\r
+ *   The base address of MDIO \r
+ */\r
+#define TARGET_MDIO_BASE    0x2c81800\r
+\r
+/**\r
+ *  @brief\r
+ *    GPIO address\r
+ */\r
+#define GPIO_GPIOPID_REG               0x02B00000\r
+#define GPIO_GPIOEMU_REG               0x02B00004\r
+#define GPIO_BINTEN_REG                        0x02B00008\r
+#define GPIO_DIR_REG                   0x02B00010\r
+#define GPIO_OUT_DATA_REG              0x02B00014\r
+#define GPIO_SET_DATA_REG              0x02B00018\r
+#define GPIO_CLEAR_DATA_REG            0x02B0001C\r
+#define GPIO_IN_DATA_REG               0x02B00020\r
+#define GPIO_SET_RIS_TRIG_REG  0x02B00024\r
+#define GPIO_CLR_RIS_TRIG_REG  0x02B00028\r
+#define GPIO_SET_FAL_TRIG_REG  0x02B0002C\r
+#define GPIO_CLR_FAL_TRIG_REG  0x02B00030\r
+\r
+/**\r
+ *  @brief\r
+ *    GPIO pin mapping \r
+ */\r
+#define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring\r
+#define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring\r
+#define NAND_NWE_GPIO_PIN      GPIO_10\r
+#define NAND_NRE_GPIO_PIN      GPIO_12\r
+#define NAND_NCE_GPIO_PIN      GPIO_13\r
+#define NAND_MODE_GPIO         GPIO_14\r
+\r
+/**\r
+ *  @brief\r
+ *      The standard NAND delay must be big enough to handle the highest possible\r
+ *      operating frequency of the device */\r
+#define TARGET_NAND_STD_DELAY                          25 // In cpu cycles\r
+\r
+/**\r
+ *  @brief\r
+ *      The base address of the I2C peripheral, and the module divisor of the cpu clock\r
+ */\r
+#define DEVICE_I2C_BASE                 0x02b04000\r
+#define DEVICE_I2C_MODULE_DIVISOR       6\r
+ \r