new pll sequence of 1.main 2.pa 3.ddr

diff --git a/src/device/c66x/c66xinit.c b/src/device/c66x/c66xinit.c
index 3080af62635a241e6c04400b3cb839c920e695dd..eb2dd36ffbe9978d0c1777cd5b4400e25b63ccc6 100755 (executable)
--- a/src/device/c66x/c66xinit.c
+++ b/src/device/c66x/c66xinit.c
@@ -33,6 +33,13 @@ void devicePllConfig (void)
                      ibl.pllConfig[ibl_MAIN_PLL].mult,
                      ibl.pllConfig[ibl_MAIN_PLL].postdiv);
 
                      ibl.pllConfig[ibl_MAIN_PLL].mult,
                      ibl.pllConfig[ibl_MAIN_PLL].postdiv);
 

+    if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+        hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+                        ibl.pllConfig[ibl_NET_PLL].prediv,
+                        ibl.pllConfig[ibl_NET_PLL].mult,
+                        ibl.pllConfig[ibl_NET_PLL].postdiv,
+                        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                        ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);

 
     if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
         hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
 
     if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
         hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),


@@ -42,15 +49,6 @@ void devicePllConfig (void)
                          ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
                          ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
 
                          ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
                          ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
 

-
-    if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
-        hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
-                        ibl.pllConfig[ibl_NET_PLL].prediv,
-                        ibl.pllConfig[ibl_NET_PLL].mult,
-                        ibl.pllConfig[ibl_NET_PLL].postdiv,
-                        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
-                        ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
-

 }
 
 
 }
 
 

diff --git a/src/hw/ddrs/emif4/emif4.c b/src/hw/ddrs/emif4/emif4.c
index ccfa122b6ab3760f067b22a34dc79df676a8fcdd..7b82f8c9709771c1131ad472909fd9ce532566ff 100755 (executable)
--- a/src/hw/ddrs/emif4/emif4.c
+++ b/src/hw/ddrs/emif4/emif4.c
@@ -106,17 +106,6 @@ SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
 
        KICK0 = KICK0_UNLOCK;
        KICK1 = KICK1_UNLOCK;
 
        KICK0 = KICK0_UNLOCK;
        KICK1 = KICK1_UNLOCK;

-       /* Adding DDR PLL code here */
-       DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
-       DDR3PLLCTL0 |= 0x00800000;      //Set BYPASS bit = 1
-       DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
-       DDR3PLLCTL0 = 0x098804C0;       //Configure PLLM, PLLD, BWADJ
-       DDR3PLLCTL1 &= ~(0x0000000F);   //Clear upper BWADJ
-       ddr3_wait(7000);                //Wait at least 5us for reset to complete
-       DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
-       ddr3_wait(70000);               //Wait >50us for PLL lock - min 500*(PLL+1) DDRCLK periods
-       DDR3PLLCTL0 &= ~(0x00800000);   //Clear BYPASS bit
-       /*End DDR PLL code */

         
        /**************** 3.3 Leveling register configuration ********************/
         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
         
        /**************** 3.3 Leveling register configuration ********************/
         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field

diff --git a/src/util/i2cConfig/i2cConfig.gel b/src/util/i2cConfig/i2cConfig.gel
index 5f6826370928623d8178b2915f977e447d8b4464..ef702969c503fff0123b155f8e411fd07eb1b4b8 100755 (executable)
--- a/src/util/i2cConfig/i2cConfig.gel
+++ b/src/util/i2cConfig/i2cConfig.gel
@@ -781,7 +781,7 @@ hotmenu setConfig_c6678_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */

-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0; 
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;


@@ -996,7 +996,7 @@ hotmenu setConfig_c6670_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL */
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL */

-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0;
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1;

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;

diff --git a/src/util/iblConfig/src/device.c b/src/util/iblConfig/src/device.c
index 5e63eb66339b37efb87a2ed493ba96a5603e5f7f..6c6c1819faa2d2ea5e64483fecb1a89ec87a9785 100644 (file)
--- a/src/util/iblConfig/src/device.c
+++ b/src/util/iblConfig/src/device.c
@@ -723,7 +723,7 @@ ibl_t c6678_ibl_config(void)
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: */
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
        /* DDR PLL: */

-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0; 
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;


@@ -940,7 +940,7 @@ ibl_t c6670_ibl_config(void)
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL */
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL */

-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0; 
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 

        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;