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raw | patch | inline | side by side (parent: 9eb0da6)
raw | patch | inline | side by side (parent: 9eb0da6)
author | Sandeep Paulraj <s-paulraj@ti.com> | |
Wed, 15 Jun 2011 19:44:25 +0000 (15:44 -0400) | ||
committer | Sandeep Paulraj <s-paulraj@ti.com> | |
Thu, 30 Jun 2011 16:04:37 +0000 (12:04 -0400) |
This commit adds support for the C64x+ SOCs in the
GPIO NAND Driver
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
GPIO NAND Driver
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/hw/nands/gpio/nandgpio.c | patch | blob | history |
index 5ca9c76a2820f0012cf8830855491adbd6e3c52f..89918305922e194ec58c1f4af180ef7f515bf112 100644 (file)
@@ -296,14 +296,27 @@ Int32 nandHwGpioDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32
*/
addr = PACK_ADDR(0x0, page, block);
- ptNandAleSet((addr >> 0u) & 0xFF); /* A0-A7 1st Cycle; column addr */
- ndelay(TARGET_NAND_STD_DELAY);
- ptNandAleSet((addr >> 9u) & 0xFF); /* A9-A16 2nd Cycle; page addr & blk */
- ndelay(TARGET_NAND_STD_DELAY);
- ptNandAleSet((addr >> 17u) & 0xFF); /* A17-A24 3rd Cycle; Block addr */
- ndelay(TARGET_NAND_STD_DELAY);
- ptNandAleSet((addr >> 25u) & 0x1); /* A25 4th Cycle; Plane addr */
- ndelay(TARGET_NAND_STD_DELAY);
+ if (hwDevInfo->pageSizeBytes == 512) {
+ ptNandAleSet((addr >> 0u) & 0xFF); /* A0-A7 1st Cycle; column addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 9u) & 0xFF); /* A9-A16 2nd Cycle; page addr & blk */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 17u) & 0xFF); /* A17-A24 3rd Cycle; Block addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 25u) & 0x1); /* A25 4th Cycle; Plane addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+ } else {
+ ptNandAleSet((addr >> 0u) & 0xFF); /* A0-A7 1st Cycle; column addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 8u) & 0x0F); /* A8-A11 2nd Cycle; page addr & blk */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 16u) & 0xFF); /* A16-A23 3rd Cycle; Block addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+ ptNandAleSet((addr >> 24u) & 0xFF); /* A24-A31 4th Cycle; Plane addr */
+ ndelay(TARGET_NAND_STD_DELAY);
+
+ ptNandCmdSet(0x30);
+ }
// Wait for Ready Busy Pin to go HIGH
Uint8 *SpareAreaBuf = NULL;
Uint8 tempSpareAreaBuf[3];
- SpareAreaBuf = data + NAND_BYTES_PER_PAGE;
+ SpareAreaBuf = data + hwDevInfo->pageSizeBytes;
/* Read the page, including the extra bytes */
ret = nandHwGpioDriverReadBytes (block, page, 0, hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes, data);
/* Perform ECC on 256 byte blocks. Three bytes of ecc per 256 byte block are used. The last
* 3 bytes are used for the last block, the previous three for the block before that, etc */
- for(i = 0; i < NAND_BYTES_PER_PAGE / ECC_BLOCK_SIZE; i++)
- {
- /* Correct ecc error for each 256 byte blocks */
- eccComputeECC(data + i * ECC_BLOCK_SIZE, eccCalc);
-
- if ( i == 0) {
- iErrors = eccCorrectData(data + (i * ECC_BLOCK_SIZE),
- (SpareAreaBuf + (i * 3)), eccCalc);
- }
-
- if (i == 1) {
- tempSpareAreaBuf[0] = SpareAreaBuf[3];
- tempSpareAreaBuf[1] = SpareAreaBuf[6];
- tempSpareAreaBuf[2] = SpareAreaBuf[7];
+ for(i = 0; i < hwDevInfo->pageSizeBytes / ECC_BLOCK_SIZE; i++)
+ {
+ /* Correct ecc error for each 256 byte blocks */
+ eccComputeECC(data + i * ECC_BLOCK_SIZE, eccCalc);
+
+ if (hwDevInfo->pageSizeBytes == 512) {
+ if ( i == 0) {
+ iErrors = eccCorrectData(data + (i * ECC_BLOCK_SIZE),
+ (SpareAreaBuf + (i * 3)), eccCalc);
+ }
+
+ if (i == 1) {
+ tempSpareAreaBuf[0] = SpareAreaBuf[3];
+ tempSpareAreaBuf[1] = SpareAreaBuf[6];
+ tempSpareAreaBuf[2] = SpareAreaBuf[7];
- iErrors = eccCorrectData(data + (i * ECC_BLOCK_SIZE),
- tempSpareAreaBuf, eccCalc);
- }
-
-// if(iErrors != ECC_SUCCESS)
-// return (NAND_ECC_FAILURE);
+ iErrors = eccCorrectData(data + (i * ECC_BLOCK_SIZE),
+ tempSpareAreaBuf, eccCalc);
+ }
+ } else {
+ iErrors = eccCorrectData(data + (i * ECC_BLOCK_SIZE),
+ (SpareAreaBuf + 40 + (i * 3)), eccCalc);
+ }
}
return (0);