Updated 6657 DDR3 config
authorCasey Smith <c-smith@ti.com>
Mon, 3 Dec 2012 17:13:58 +0000 (12:13 -0500)
committerCasey Smith <c-smith@ti.com>
Mon, 3 Dec 2012 17:13:58 +0000 (12:13 -0500)
src/util/i2cConfig/i2cConfig.gel
src/util/iblConfig/src/device.c

index 4d373918db5427b22aae448ff612c04192f24900..fef60142f1381bee99320e6c100aa9976cf3a5ba 100755 (executable)
@@ -1213,7 +1213,7 @@ hotmenu setConfig_c6657_main()
        /* DDR PLL: */
        ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 3;
-       ibl.pllConfig[ibl_DDR_PLL].mult           = 40;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 80;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;
 
index 58fb3def5dac634686220d16d526d47f4f51b013..87e5d46e4d859bccacc9109098cea138b24e5728 100755 (executable)
@@ -1166,7 +1166,7 @@ ibl_t c6657_ibl_config(void)
        /* DDR PLL: */
        ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 3;
-       ibl.pllConfig[ibl_DDR_PLL].mult           = 40;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 80;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
        ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;