summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 4f7d6ae)
raw | patch | inline | side by side (parent: 4f7d6ae)
| author | Mike Line <m-line1@ti.com> | |
| Fri, 14 Jan 2011 18:21:40 +0000 (13:21 -0500) | ||
| committer | Mike Line <m-line1@ti.com> | |
| Fri, 14 Jan 2011 18:21:40 +0000 (13:21 -0500) |
31 files changed:
diff --git a/src/cfg/c661x/iblcfg.h b/src/cfg/c661x/iblcfg.h
index f77ce5125c8d45d404ec25128b7819a7693a156a..c509fb7b5d313826a8281a843c37b13a064dbb39 100644 (file)
--- a/src/cfg/c661x/iblcfg.h
+++ b/src/cfg/c661x/iblcfg.h
/**
* @brief The default location for the spi map information can be overridden during make
*/
-#ifndef IBL_CFG_SPI_MAP_TABLE_DATA_ADDR
- #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR 0x400
+#ifndef IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW
+ #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW 0x400
+#endif
+
+#ifndef IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+ #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW 0
#endif
index a04a33172c4443f4fb2d981788b1360b27180595..9ad2feea13eab6b2fd8e2d07c09b55817ff0ebbf 100644 (file)
--- a/src/device/c661x/c661x.c
+++ b/src/device/c661x/c661x.c
}
-/**
- * @brief Power up a peripheral
- *
- * @details
- * Boot peripherals are powered up
- */
-int32 devicePowerPeriph (int32 modNum)
-{
- int32 ret;
-
- /* If the input value is < 0 there is nothing to power up */
- if (modNum < 0)
- return (0);
-
-
- if (modNum >= TARGET_PWR_MAX_MOD)
- return (-1);
-
-
- /* Note that if the sgmii power enable is requested the PA must be
- * powered up first */
- if (modNum == TARGET_PWR_ETH(x)) {
- ret = (int32)pscEnableModule (TARGET_PWR_PA);
- if (ret != 0)
- return (ret);
- }
-
- return ((int32)pscEnableModule(modNum));
-
-}
-
-/**
- * @brief return the PSC module number for SPI
- */
-int32 deviceSpiPscNum (void)
-{
- uint32 v;
-
- /* SPI is module number 3 only on the c6618. On the c6616 the SPI is in the
- * always on domain */
- v = *((Uint32 *)DEVICE_JTAG_ID_REG);
- if (v == DEVICE_C6618_JTAG_ID_VAL)
- return (3);
-
- return (-1); /* A negative number indicates the always on domain */
-}
-
-
/**
* @brief Enable EMIF25 or SPI interface to the NAND
index 0eca68dfce21da66297b5c3ce2a7816c150cf494..1fe5f145b7479e0f930339c6dba94b2757180a63 100644 (file)
} /* chipPllExternalMult */
+/**
+ * @brief return the PSC module number for SPI
+ */
+int32 deviceSpiPscNum (void)
+{
+ uint32 v;
+
+ /* SPI is module number 3 only on the c6618. On the c6616 the SPI is in the
+ * always on domain */
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ if (v == DEVICE_C6618_JTAG_ID_VAL)
+ return (3);
+
+ return (-1); /* A negative number indicates the always on domain */
+}
+
+/**
+ * @brief Power up a peripheral
+ *
+ * @details
+ * Boot peripherals are powered up
+ */
+int32 devicePowerPeriph (int32 modNum)
+{
+ int32 ret;
+
+ /* If the input value is < 0 there is nothing to power up */
+ if (modNum < 0)
+ return (0);
+
+
+ if (modNum >= TARGET_PWR_MAX_MOD)
+ return (-1);
+
+
+ /* Note that if the sgmii power enable is requested the PA must be
+ * powered up first */
+ if (modNum == TARGET_PWR_ETH(x)) {
+ ret = (int32)pscEnableModule (TARGET_PWR_PA);
+ if (ret != 0)
+ return (ret);
+ }
+
+ return ((int32)pscEnableModule(modNum));
+
+}
+
index 09492b8b9c906a1144d631fa5abc3182ebf563c1..bdf6e8534537b832b332078a0ded2006783b4add 100644 (file)
#define TIBOOT_ERR_HIBERNATION_ADDR_MISALIGNED -2
#define TIBOOT_ERR_HIBERNATION_ADDR_INVALID -3
+/* Boot mode values */
+#define BOOT_MODE_I2C 40
+#define BOOT_MODE_SPI 50
+
#endif /* __TIBOOT_H__ */
index 1eb04f4f0b15193c5fc7e89e17ac865ed1a736be..aeb36f405869d90a13efca78a3784875204eeab5 100644 (file)
else
ifeq ($(TARGET),c661x)
CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c cpsw.c qm.c cpdma.c pa.c sgmii.c serdes.c gmacsl.c emif4.c
- CSRC+= nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c
+ CSRC+= nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
else
CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c cfgpll.c cfgpll2.c
- CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c
+ CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
endif
endif
endif
index d709d113c8f9aeae69df48e3469485522c1a7d18..cf99567b6a5b0b97323817863684e190b95e2032 100644 (file)
secctl = secctl | PLL_REG_SECCTL_FIELD_BYPASS;
DEVICE_REG32_W (pllBase + PLL_REG_SECCTL, secctl);
+
+ /* Reset the PLL, wait at least 5 us, release reset */
+ ctl = ctl | 2;
+ DEVICE_REG32_W (pllBase + PLL_REG_CTL, ctl);
+ hw_pll_delay (500 * 5 * 20);
+
+ ctl = ctl & ~2;
+ DEVICE_REG32_W (pllBase + PLL_REG_CTL, ctl);
+ hw_pll_delay (500 * 5 * 20);
+
/* Reset the PLL */
ctl = ctl | PLL_REG_CTL_FIELD_PLLRST;
DEVICE_REG32_W (pllBase + PLL_REG_CTL, ctl);
diff --git a/src/hw/spi/spi.c b/src/hw/spi/spi.c
index fb0ba45562e0ef60e6e514213aa604c45849c4a6..d9a351425ac37f8c736ac0a6b6e0d6d1730009e4 100644 (file)
--- a/src/hw/spi/spi.c
+++ b/src/hw/spi/spi.c
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
/**********************************************************************************************
* FILE PURPOSE: The SPI boot driver
**********************************************************************************************
diff --git a/src/hw/spi/spi_api.h b/src/hw/spi/spi_api.h
index 6a80a79bb534b06b67fe84ab41253d0701755d63..247931bb435818a4e2911231b5e09867bfb2700e 100644 (file)
--- a/src/hw/spi/spi_api.h
+++ b/src/hw/spi/spi_api.h
SINT16 hwSpiConfig (spiConfig_t *spiCfg);
SINT16 hwSpiRead (UINT32 addr, UINT16 sizeBytes, UINT8 *data);
+void hwSpiEnableXfer (UINT32 port);
+void hwSpiDisableXfer (UINT32 port);
/* Return values */
#define SPI_INVALID_ADDR_WIDTH -1
diff --git a/src/hw/spi/spi_loc.h b/src/hw/spi/spi_loc.h
index 296a72f624a28c550b880b26338b291c02a4fb92..00c3f43d69c10e12fe1158d212a33d90ca8b2fd8 100644 (file)
--- a/src/hw/spi/spi_loc.h
+++ b/src/hw/spi/spi_loc.h
/* Commands */
-#define SPI_COMMAND_READ 3
+#define SPI_COMMAND_WRITE 0x02
+#define SPI_COMMAND_READ 0x03
+#define SPI_COMMAND_READ_STATUS 0x05
+#define SPI_COMMAND_WRITE_ENABLE 0x06
+#define SPI_COMMAND_ERASE_SECTOR 0x20
+
+SINT16 hw_spi_xfer (UINT16 nbytes, UINT8 *dataOut, UINT8 *dataIn, spiConfig_t *cfg, BOOL terminate);
#endif /* _SPI_LOC_H */
diff --git a/src/hw/spi/spiutil.c b/src/hw/spi/spiutil.c
--- /dev/null
+++ b/src/hw/spi/spiutil.c
@@ -0,0 +1,53 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "types.h"
+#include "device.h"
+#include "spi_api.h"
+#include "spi_loc.h"
+
+
+void hwSpiEnableXfer (UINT32 port)
+{
+ DEVICE_REG32_W (DEVICE_SPI_BASE(port) + SPI_REG_SPIGCR1, SPI_REG_VAL_SPIGCR1_XFER);
+}
+
+void hwSpiDisableXfer (UINT32 port)
+{
+ DEVICE_REG32_W (DEVICE_SPI_BASE(port) + SPI_REG_SPIGCR1, SPI_REG_VAL_SPIGCR1_XFER_DISABLE);
+}
+
+
+
index 25a6812504e8642a3c6e2546d07b0d58eaaf0163..75e5509d7b92e5f6d4f8f556e4da86072f580502 100644 (file)
--- a/src/main/iblinitspinor.c
+++ b/src/main/iblinitspinor.c
/* Read the SPI mapping information from the nor flash */
for (;;) {
- if (hwSpiRead (IBL_CFG_SPI_MAP_TABLE_DATA_ADDR, /* The address on the flash of the data mapping */
- sizeof(iblBootMap_t), /* The number of bytes to read */
- (UINT8 *)&map) /* Where to store the data */
+ if (hwSpiRead ((IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW << 16) | /* The address on the flash of the data mapping */
+ IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW,
+ sizeof(iblBootMap_t), /* The number of bytes to read */
+ (UINT8 *)&map) /* Where to store the data */
== 0) {
diff --git a/src/make/Makefile b/src/make/Makefile
index 131aa387c3378898223a422d7ca294fb6b984302..c106746c7b64b2b064b165c50f9bcff36ff9ee1d 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
# The SPI configuration parameters
ifndef SPI_MODE
- SPI_MODE=3
+ SPI_MODE=1
endif
ifndef SPI_ADDR_WIDTH
make -f makestg1 ARCH=c64x TARGET=c6457 I2C_BUS_ADDR=0x51 COMPACT_I2C=yes ENDIAN_MODE=big CEXCLUDES='ELF NAND_GPIO BIS' I2C_SIZE_BYTES=0x8000 c6457
cp ibl_c6457/i2crom.dat ibl_c6457/i2crom_0x51.dat
-# The 6618 EVM
-evm_c6618:
- make -f makestg1 ARCH=c64x TARGET=c661x I2C_BUS_ADDR=0x50 ENDIAN_MODE=little CEXCLUDES= DEBUG=YES SPI_DEFS='$(SPI_DEFS)' c661x
+# The 6608 EVM
+EVM_6608_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
+
+evm_c6608:
+ make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x50 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
test_c661x:
make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 COMPACT_I2C=no c661x
diff --git a/src/make/ibl_c661x/ibl_init_objs_template.inc b/src/make/ibl_c661x/ibl_init_objs_template.inc
index e79352ffa56b9b25a5f99e9b34d9125b503b9bcb..414795ffae809920823bc9f9627908ec9aa5bbaa 100644 (file)
../interp/c64x/make/btblwrap.ENDIAN_TAG.oc
../interp/c64x/make/btblpr.ENDIAN_TAG.oc
../interp/c64x/make/gem.ENDIAN_TAG.oc
+../hw/c64x/make/psc.ENDIAN_TAG.oc
#ifndef EXCLUDE_I2C
../main/c64x/make/ibliniti2c.ENDIAN_TAG.oc
diff --git a/src/make/makestg2 b/src/make/makestg2
index 8ebea6614d2906a531ca132898e96f01099ce752..350fa4198231f80cd9be87cb52fd84644e86fff4 100644 (file)
--- a/src/make/makestg2
+++ b/src/make/makestg2
I2C_DEFS+= -DPAD_FILE_ID_1=1
I2C_DEFS+= -DEXE_FILE_2=$(I2C_BE_FILE)
I2C_DEFS+= -DPAD_FILE_ID_2=2
+
+ SPI_CFG+= -DINIT_EXE_FILE=$(I2C_INIT_LE_FILE)
+ SPI_CFG+= -DEXE_FILE_1=$(I2C_LE_FILE)
+ SPI_CFG+= -DPAD_FILE_ID_1=1
+ SPI_CFG+= -DEXE_FILE_2=$(I2C_BE_FILE)
+ SPI_CFG+= -DPAD_FILE_ID_2=2
+
else
I2C_DEFS+= -DPAD_FILE_ID_1=1
I2C_DEFS+= -DPAD_FILE_ID_2=1
+ SPI_CFG+= -DPAD_FILE_ID_1=1
+ SPI_CFG+= -DPAD_FILE_ID_2=1
+
ifeq ($(I2CROM),little_endian)
I2C_DEFS+= -DINIT_EXE_FILE=$(I2C_INIT_LE_FILE)
I2C_DEFS+= -DEXE_FILE_1=$(I2C_LE_FILE)
I2C_DEFS+= -DEXE_FILE_2='""'
+
+ SPI_CFG+= -DINIT_EXE_FILE=$(I2C_INIT_LE_FILE)
+ SPI_CFG+= -DEXE_FILE_1=$(I2C_LE_FILE)
+ SPI_CFG+= -DEXE_FILE_2='""'
+
else
I2C_DEFS+= -DINIT_EXE_FILE=$(I2C_INIT_BE_FILE)
I2C_DEFS+= -DEXE_FILE_1='""'
I2C_DEFS+= -DEXE_FILE_2=$(I2C_BE_FILE)
+
+ SPI_CFG+= -DINIT_EXE_FILE=$(I2C_INIT_BE_FILE)
+ SPI_CFG+= -DEXE_FILE_1='""'
+ SPI_CFG+= -DEXE_FILE_2=$(I2C_BE_FILE)
+
endif
endif
spiRom:
@echo Making SPI ROM
+ $(CC) -ppo -I../cfg/$(TARGET) $(SPI_CFG) ibl_$(TARGET)/$@.map.pre
+ ../util/romparse/romparse $(COMPACT) -fill 0xff -rom_base 0 ibl_$(TARGET)/$@.map.pp
+ $(CP) i2crom.ccs ibl_$(TARGET)/$@.ccs
+ $(CP) i2crom.ccs ibl_$(TARGET)/$@.dat
make -C $(IBL_ROOT)/$@/$(ARCH)/make CDEFS='$(MAINDEFS) $(SPI_CFG)' $@
utils:
+ make -C $(IBL_ROOT)/util/spiWrite TARGET=$(TARGET) SPI_DEFS='$(SPI_DEFS)' MAINDEFS='$(MAINDEFS) $(SPI_CFG)' $(TARGET)
+ make -C $(IBL_ROOT)/util/spiConfig TARGET=$(TARGET) SPI_DEFS='$(SPI_DEFS)' MAINDEFS='$(MAINDEFS) $(SPI_CFG)' $(TARGET)
make -C $(IBL_ROOT)/util/btoccs
make -C $(IBL_ROOT)/util/romparse TARGET=$(TARGET)
make -C $(IBL_ROOT)/util/i2cRead TARGET=$(TARGET) $(TARGET)
index 5edd340c7e9cb7c2301fb958a87edae4da74f667..d4aa56204ef212fefefb626249e5302ee006d2dc 100644 (file)
MEMORY
{
STACK : origin = 0x810000 length = 0x0400
- TEXT : origin = 0x810400 length = 0x8000
- DATA : origin = 0x818400 length = 0x0800
- SYSMEM : origin = 0x809000 length = 0x0800
+ TEXT : origin = 0x810400 length = 0x9000
+ DATA : origin = 0x819400 length = 0x0800
+ SYSMEM : origin = 0x80a000 length = 0x0800
}
SECTIONS
index 63b69434d92493beeb4e20a5e88cbed28a92b9db..09d218e3ee87d99812d5542bbb65aa79ce9abafd 100644 (file)
ifeq ($(TARGET),c661x)
PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc
PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
+ PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc
else
PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
endif
.PHONY: i2cparam.cmd
$(DEVICES): gen_cdefdep $(MODULES) $(CFG_MODULES) $(OBJS) i2cparam.cmd
- $(LD) -o i2cparam_$(TARGET)_$(IEXT).out -m i2cparam_$(TARGET)_$(IEXT).map i2cparam.$(IEXT).oc ../../hw/c64x/make/i2c.$(IEXT).oc $(PLL_OBJS) $(TFILES) i2cparam.cmd $(RTLIBS)
+ $(LD) -o i2cparam_$(TARGET)_$(IEXT).out -m i2cparam_$(TARGET)_$(IEXT).map i2cparam.$(IEXT).oc ../../hw/c64x/make/i2c.$(IEXT).oc $(PLL_OBJS) $(PSC_OBJS) $(TFILES) i2cparam.cmd $(RTLIBS)
$(MODULES):
@echo making $@
index dff52234f7d6730bdda1816c2175329c21e846db..d913ef5b240d812b559e436240eeb31a31c562e6 100644 (file)
ifeq ($(TARGET),c661x)
PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc
PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
+ PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc
else
PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
endif
$(DEVICES): gen_cdefdep $(MODULES) $(CFG_MODULES) $(OBJS) i2cWrite.cmd
- $(LD) -o i2cWrite_$(IEXT).out -m i2cWrite_$(IEXT).map i2cWrite.$(IEXT).oc ../../hw/c64x/make/i2c.$(IEXT).oc $(PLL_OBJS) $(TFILES) i2cWrite.cmd $(RTLIBS)
+ $(LD) -o i2cWrite_$(IEXT).out -m i2cWrite_$(IEXT).map i2cWrite.$(IEXT).oc ../../hw/c64x/make/i2c.$(IEXT).oc $(PLL_OBJS) $(PSC_OBJS) $(TFILES) i2cWrite.cmd $(RTLIBS)
$(MODULES):
index 0fd8bcfdd78dfc86d9d261149bf7c915dd090d00..1b8dc3400bbe22eaf9e449168b5f476a9b4a6c29 100644 (file)
char *inputFile;
int compact = 0;
+/*************************************************************************************
+ * Declaration: The value used to fill gaps in the file. For some devices this
+ * value must be set to 0xff so subsequent writing to these gaps will work
+ *************************************************************************************/
+unsigned char fillVal = 0;
+
/*************************************************************************************
* FUNCTION PURPOSE: flex/bison required support functions.
/* The length must be set. Currently this program only supports I2C mode, so the
* length is fixed */
+
current_table.common.length = 30;
+
+ #ifdef c661x
+ if (current_table.common.boot_mode == BOOT_MODE_SPI)
+ current_table.common.length = sizeof(BOOT_PARAMS_SPI_T);
+ else
+ current_table.common.length = sizeof(BOOT_PARAMS_I2C_T);
+ #endif
+
current_table.common.checksum = 0;
/* Copy the table */
case MY_I2C_ID: current_table.i2c.my_i2c_id = value;
break;
- case CORE_FREQ_MHZ: current_table.i2c.core_freq_mhz = value;
+ case CORE_FREQ_MHZ:
+ #ifdef c661x
+ if (current_table.common.boot_mode = BOOT_MODE_SPI) {
+ current_table.spi.cpuFreqMhz = value;
+ break;
+ }
+ #endif
+
+ current_table.i2c.core_freq_mhz = value;
break;
case I2C_CLK_FREQ_KHZ: current_table.i2c.i2c_clk_freq_khz = value;
#endif
#ifdef c661x
- case SWPLL_PREDIV: current_table.i2c.swPllCfg_lsw &= 0x00ff;
- current_table.i2c.swPllCfg_lsw |= ((value & 0xff) << 16);
+ case SWPLL_PREDIV: current_table.common.swPllCfg_lsw &= 0x00ff;
+ current_table.common.swPllCfg_lsw |= ((value & 0xff) << 16);
break;
- case SWPLL_MULT: current_table.i2c.swPllCfg_msw &= 0xc000;
- current_table.i2c.swPllCfg_msw |= (value & 0x3fff);
+ case SWPLL_MULT: current_table.common.swPllCfg_msw &= 0xc000;
+ current_table.common.swPllCfg_msw |= (value & 0x3fff);
break;
- case SWPLL_POSTDIV: current_table.i2c.swPllCfg_lsw &= 0xff00;
- current_table.i2c.swPllCfg_lsw |= (value & 0xff);
+ case SWPLL_POSTDIV: current_table.common.swPllCfg_lsw &= 0xff00;
+ current_table.common.swPllCfg_lsw |= (value & 0xff);
break;
- case SWPLL_FLAGS: current_table.i2c.swPllCfg_msw &= 0x3fff;
- current_table.i2c.swPllCfg_msw |= ((value & 0x3) << 14);
+ case SWPLL_FLAGS: current_table.common.swPllCfg_msw &= 0x3fff;
+ current_table.common.swPllCfg_msw |= ((value & 0x3) << 14);
break;
#endif
break;
+#ifdef c661x
+ case N_PINS: current_table.spi.nPins = value;
+ break;
+
+ case MODE: current_table.spi.mode = value;
+ break;
+
+ case C2T_DELAY: current_table.spi.c2tdelay = value;
+ break;
+
+ case BUS_FREQ_MHZ: current_table.spi.busFreqMhz = value;
+ break;
+
+ case BUS_FREQ_KHZ: current_table.spi.busFreqKhz = value;
+ break;
+
+ case ADDR_WIDTH: current_table.spi.addrWidth = value;
+ break;
+
+ case CSEL: current_table.spi.csel = value;
+ break;
+
+#endif
+
default:
fprintf (stderr, "romparse: Invalid assignment in section specification (line %d)\n", line);
break;
@@ -738,7 +785,7 @@ unsigned int imagePad (unsigned int base, unsigned int start, unsigned char *ima
}
for (i = base; i < desired; i++)
- image[i-start] = 0;
+ image[i-start] = fillVal;
return (desired);
* been tagged it means that this is an i2c program load */
for (i = 0; i < NUM_BOOT_PARAM_TABLES; i++) {
for (j = 0; j < NUM_BOOT_PARAM_TABLES; j++) {
- if (progFile[i].tag[j] >= 0)
+ if (progFile[i].tag[j] >= 0) {
+
+ #ifdef c661x
+ if (boot_params[progFile[i].tag[j]].common.boot_mode == BOOT_MODE_SPI) {
+ boot_params[progFile[i].tag[j]].spi.read_addr_lsw = (progFile[i].addressBytes & 0xffff);
+ boot_params[progFile[i].tag[j]].spi.read_addr_msw = (progFile[i].addressBytes >> 16) & 0xffff;
+ continue;
+ }
+ #endif
+
boot_params[progFile[i].tag[j]].i2c.dev_addr = (progFile[i].addressBytes & 0xffff);
+ }
}
}
exit (-1);
}
+ memset (image, fillVal, (base - i2cRomStart));
+
/* Write out the boot parameter tables. 0x80 bytes will be written out.
* There are 16 bits in every parameter field, which is why the index
* is from 0 to 0x40 */
int i;
if (argc < 2) {
- fprintf (stderr, "usage: %s [-compact] [-rom_base x] inputfile\n", argv[0]);
+ fprintf (stderr, "usage: %s [-compact] [-rom_base x] [-fill <fillval>] inputfile\n", argv[0]);
return (-1);
}
i2cRomBase = readVal (argv[i+1]);
i += 2;
+ } else if (!strcmp (argv[i], "-fill")) {
+ fillVal = readVal (argv[i+1]);
+ i += 2;
+
} else {
if (inputFile != NULL) {
- fprintf (stderr, "usage: %s [-compact] inputfile\n", argv[0]);
+ fprintf (stderr, "usage: %s [-compact] [-rom_base x] [-fill <fillval>] inputfile\n", argv[0]);
return (-1);
}
index bed2a363ccc66c11abb20c694036011cb058b80f..bb7a715f33628bbc368c49b41e1f145c8eb4725e 100644 (file)
align { yylval = ALIGN; return (ALIGN); }
len { yylval = LENGTH; return (LENGTH); }
pad_file_id { yylval = PAD_FILE_ID; return (PAD_FILE_ID); }
-sw_pll_prediv { yylval = SWPLL_PREDIV; return (SWPLL_PREDIV); }
-sw_pll_mult { yylval = SWPLL_MULT; return (SWPLL_MULT); }
-sw_pll_postdiv { yylval = SWPLL_POSTDIV; return (SWPLL_POSTDIV); }
-sw_pll_flags { yylval = SWPLL_FLAGS; return (SWPLL_FLAGS); }
+sw_pll_prediv { yylval = SWPLL_PREDIV; return (SWPLL_PREDIV); }
+sw_pll_mult { yylval = SWPLL_MULT; return (SWPLL_MULT); }
+sw_pll_postdiv { yylval = SWPLL_POSTDIV; return (SWPLL_POSTDIV); }
+sw_pll_flags { yylval = SWPLL_FLAGS; return (SWPLL_FLAGS); }
+addr_width { yylval = ADDR_WIDTH; return (ADDR_WIDTH); }
+n_pins { yylval = N_PINS; return (N_PINS); }
+mode { yylval = MODE; return (MODE); }
+c2t_delay { yylval = C2T_DELAY; return (C2T_DELAY); }
+bus_freq_mhz { yylval = BUS_FREQ_MHZ; return (BUS_FREQ_MHZ); }
+bus_freq_khz { yylval = BUS_FREQ_KHZ; return (BUS_FREQ_KHZ); }
+csel { yylval = CSEL; return (CSEL); }
[0-9]+ { yylval = atoi(yytext); return (VALUE); }
index 9049218ce055c48fa3821829c4f5d33b4eb6b53a..824f0e52c188325512bd1a23684b345b2ec15799 100644 (file)
%token EXE_FILE PCI_PARMS NEXT_DEV_ADDR NEXT_DEV_ADDR_EXT ADDRESS_DELAY SWPLL
%token DEV_ADDR_EXT DEV_ADDR LAYOUT ALIGN PAD LENGTH PAD_FILE_ID
%token SWPLL_PREDIV SWPLL_MULT SWPLL_POSTDIV SWPLL_FLAGS
+%token ADDR_WIDTH N_PINS MODE C2T_DELAY BUS_FREQ_MHZ BUS_FREQ_KHZ CSEL
%%
promspec : segment
| SWPLL_MULT { $$=$1; }
| SWPLL_POSTDIV { $$=$1; }
| SWPLL_FLAGS { $$=$1; }
+ | ADDR_WIDTH { $$=$1; }
+ | N_PINS { $$=$1; }
+ | MODE { $$=$1; }
+ | C2T_DELAY { $$=$1; }
+ | BUS_FREQ_MHZ { $$=$1; }
+ | BUS_FREQ_KHZ { $$=$1; }
+ | CSEL { $$=$1; }
;
%%
diff --git a/src/util/spiConfig/Makefile b/src/util/spiConfig/Makefile
--- /dev/null
@@ -0,0 +1,69 @@
+#*
+#*
+#* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#*
+#*
+#* Redistribution and use in source and binary forms, with or without
+#* modification, are permitted provided that the following conditions
+#* are met:
+#*
+#* Redistributions of source code must retain the above copyright
+#* notice, this list of conditions and the following disclaimer.
+#*
+#* Redistributions in binary form must reproduce the above copyright
+#* notice, this list of conditions and the following disclaimer in the
+#* documentation and/or other materials provided with the
+#* distribution.
+#*
+#* Neither the name of Texas Instruments Incorporated nor the names of
+#* its contributors may be used to endorse or promote products derived
+#* from this software without specific prior written permission.
+#*
+#* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#*
+
+
+#**************************************************************
+#* FILE PURPOSE: Top level make for the spi parameter writer
+#**************************************************************
+#* FILE NAME: Makefile
+#*
+#* DESCRIPTION: Builds the program to write the parameter table
+#* to the spi rom
+#*
+#***************************************************************
+
+DEVICES= c6455 c6472 c6474 c6474l c6457 c661x
+
+all:
+ @echo must specify a target [ $(DEVICES) ]
+
+# Default options that can be overwridden on the command line
+ifndef ENDIAN
+ ENDIAN= little
+endif
+
+export ENDIAN
+
+
+$(DEVICES):
+ make -f makestg2 ARCH=c64x TARGET=$@ $@
+
+
+clean:
+ make -f makestg2 clean2 ARCH=c64x
+
+
+
+
+
diff --git a/src/util/spiConfig/i2cConfig.gel b/src/util/spiConfig/i2cConfig.gel
--- /dev/null
@@ -0,0 +1,784 @@
+#define TRUE 1
+#define FALSE 0
+
+#define ibl_MAGIC_VALUE 0xCEC11EBB
+
+#define ibl_HIGHEST_PRIORITY 1
+#define ibl_LOWEST_PRIORITY 10
+#define ibl_DEVICE_NOBOOT 20
+
+#define ibl_PORT_SWITCH_ALL -2
+
+#define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
+ array[1]=(i1); \
+ array[2]=(i2); \
+ array[3]=(i3)
+
+#define ibl_BOOT_MODE_TFTP 10
+#define ibl_BOOT_MODE_NAND 11
+#define ibl_BOOT_MODE_NOR 12
+#define ibl_BOOT_MODE_NONE 13
+
+
+#define ibl_BOOT_FORMAT_AUTO 0
+#define ibl_BOOT_FORMAT_NAME 1
+#define ibl_BOOT_FORMAT_BIS 2
+#define ibl_BOOT_FORMAT_COFF 3
+#define ibl_BOOT_FORMAT_ELF 4
+#define ibl_BOOT_FORMAT_BBLOB 5
+#define ibl_BOOT_FORMAT_BTBL 6
+
+#define ibl_MAIN_PLL 0
+#define ibl_DDR_PLL 1
+#define ibl_NET_PLL 2
+
+#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
+#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
+#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
+#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
+#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
+#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
+#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
+#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
+#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
+#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
+#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
+#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
+#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
+#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
+#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
+#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
+#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
+#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
+#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
+#define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
+#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
+#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
+#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
+#define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
+
+/* @} */
+
+menuitem "EVM c6472 IBL";
+
+hotmenu setConfig_c6472()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_AUTO;
+
+
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,21);
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
+
+ /* Leave the hardware address as 0 so the e-fuse value will be used */
+
+
+
+
+ ibl.ethConfig[0].ethInfo.fileName[0] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[1] = 'e';
+ ibl.ethConfig[0].ethInfo.fileName[2] = 's';
+ ibl.ethConfig[0].ethInfo.fileName[3] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[4] = '.';
+ ibl.ethConfig[0].ethInfo.fileName[5] = 'o';
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'u';
+ ibl.ethConfig[0].ethInfo.fileName[7] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[8] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[9] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ /* For port 1 use bootp */
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;
+ ibl.ethConfig[1].port = 1;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[1].doBootp = TRUE;
+ ibl.ethConfig[1].useBootpServerIp = TRUE;
+ ibl.ethConfig[1].useBootpFileName = TRUE;
+ ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_AUTO;
+
+
+ /* SGMII not present */
+ ibl.sgmiiConfig[0].adviseAbility = 0;
+ ibl.sgmiiConfig[0].control = 0;
+ ibl.sgmiiConfig[0].txConfig = 0;
+ ibl.sgmiiConfig[0].rxConfig = 0;
+ ibl.sgmiiConfig[0].auxConfig = 0;
+
+ ibl.sgmiiConfig[1].adviseAbility = 0;
+ ibl.sgmiiConfig[1].control = 0;
+ ibl.sgmiiConfig[1].txConfig = 0;
+ ibl.sgmiiConfig[1].rxConfig = 0;
+ ibl.sgmiiConfig[1].auxConfig = 0;
+
+
+ /* Leave the hardware address as 0 so the e-fuse value will be used */
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+ /* Leave all remaining fields as 0 since bootp will fill them in */
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will */
+ /* stop when the ftp reaches the end of the file */
+
+ ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
+
+
+ /* Nand boot is disabled */
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+ ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_AUTO;
+
+ ibl.nandConfig.nandInfo.busWidthBits = 8;
+ ibl.nandConfig.nandInfo.pageSizeBytes = 2048;
+ ibl.nandConfig.nandInfo.pageEccBytes = 64;
+ ibl.nandConfig.nandInfo.pagesPerBlock = 64;
+ ibl.nandConfig.nandInfo.totalBlocks = 1024;
+
+ ibl.nandConfig.nandInfo.addressBytes = 4;
+ ibl.nandConfig.nandInfo.lsbFirst = TRUE;
+ ibl.nandConfig.nandInfo.blockOffset = 22;
+ ibl.nandConfig.nandInfo.pageOffset = 16;
+ ibl.nandConfig.nandInfo.columnOffset = 0;
+
+ ibl.nandConfig.nandInfo.resetCommand = 0xff;
+ ibl.nandConfig.nandInfo.readCommandPre = 0;
+ ibl.nandConfig.nandInfo.readCommandPost = 0x30;
+ ibl.nandConfig.nandInfo.postCommand = TRUE;
+
+}
+
+
+menuitem "EVM c6474 Mez IBL";
+
+hotmenu setConfig_c6474()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+ ibl.ethConfig[0].ethInfo.fileName[0] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[1] = 'e';
+ ibl.ethConfig[0].ethInfo.fileName[2] = 's';
+ ibl.ethConfig[0].ethInfo.fileName[3] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[4] = '.';
+ ibl.ethConfig[0].ethInfo.fileName[5] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'o';
+ ibl.ethConfig[0].ethInfo.fileName[8] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[9] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
+
+ /* There is no port 1 on the 6474 */
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
+
+ /* SGMII is present */
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x26;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+ /* Nand boot is disabled */
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6474 Lite EVM IBL";
+
+hotmenu setConfig_c6474lite()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 533 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+ ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
+ ibl.ethConfig[0].ethInfo.fileName[1] = '6';
+ ibl.ethConfig[0].ethInfo.fileName[2] = '4';
+ ibl.ethConfig[0].ethInfo.fileName[3] = '7';
+ ibl.ethConfig[0].ethInfo.fileName[4] = '4';
+ ibl.ethConfig[0].ethInfo.fileName[5] = 'l';
+ ibl.ethConfig[0].ethInfo.fileName[6] = '-';
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'l';
+ ibl.ethConfig[0].ethInfo.fileName[8] = 'e';
+ ibl.ethConfig[0].ethInfo.fileName[9] = '.';
+ ibl.ethConfig[0].ethInfo.fileName[10] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[11] = 'i';
+ ibl.ethConfig[0].ethInfo.fileName[12] = 'n';
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
+
+ /* There is no port 1 on the 6474 Lite EVM */
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
+
+ /* SGMII is present */
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000e23;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x26;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+ /* This board has NAND. We will enable later */
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6457 EVM IBL";
+
+hotmenu setConfig_c6457()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x3d44c742; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,115);
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
+
+ /* Set the hardware address as 0 so the e-fuse value will be used */
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+ ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
+ ibl.ethConfig[0].ethInfo.fileName[1] = '6';
+ ibl.ethConfig[0].ethInfo.fileName[2] = '4';
+ ibl.ethConfig[0].ethInfo.fileName[3] = '5';
+ ibl.ethConfig[0].ethInfo.fileName[4] = '7';
+ ibl.ethConfig[0].ethInfo.fileName[5] = '-';
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
+ ibl.ethConfig[0].ethInfo.fileName[8] = '.';
+ ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
+ ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ /* There is no port 1 on the 6457 Lite EVM */
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
+
+ /* SGMII is present */
+ ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+ ibl.sgmiiConfig[0].control = 0x20;
+ ibl.sgmiiConfig[0].txConfig = 0x00000e23;
+ ibl.sgmiiConfig[0].rxConfig = 0x00081023;
+ ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x26;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+ /* This board has NAND. We will enable later */
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6455 IBL";
+
+hotmenu setConfig_c6455()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration. The values are for DDR at 500 MHz */
+ ibl.ddrConfig.configDdr = TRUE;
+
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
+
+ /* Ethernet configuration for port 0 */
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+
+ /* Bootp is disabled. The server and file name are provided here */
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
+
+ /* There is no e-fuse mac address. A value must be assigned */
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 10;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 224;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 166;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 102;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 87;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 25;
+
+
+ ibl.ethConfig[0].ethInfo.fileName[0] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[1] = 'e';
+ ibl.ethConfig[0].ethInfo.fileName[2] = 's';
+ ibl.ethConfig[0].ethInfo.fileName[3] = 't';
+ ibl.ethConfig[0].ethInfo.fileName[4] = '.';
+ ibl.ethConfig[0].ethInfo.fileName[5] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'o';
+ ibl.ethConfig[0].ethInfo.fileName[8] = 'b';
+ ibl.ethConfig[0].ethInfo.fileName[9] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+ /* Even though the entire range of DDR2 is chosen, the load will
+ * stop when the ftp reaches the end of the file */
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
+
+ /* There is no ethernet port 1 */
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
+
+
+ /* SGMII not present */
+ ibl.sgmiiConfig[0].adviseAbility = 0;
+ ibl.sgmiiConfig[0].control = 0;
+ ibl.sgmiiConfig[0].txConfig = 0;
+ ibl.sgmiiConfig[0].rxConfig = 0;
+ ibl.sgmiiConfig[0].auxConfig = 0;
+
+ ibl.sgmiiConfig[1].adviseAbility = 0;
+ ibl.sgmiiConfig[1].control = 0;
+ ibl.sgmiiConfig[1].txConfig = 0;
+ ibl.sgmiiConfig[1].rxConfig = 0;
+ ibl.sgmiiConfig[1].auxConfig = 0;
+
+
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 0;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
+
+
+ /* Nand boot is disabled */
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+
+menuitem "EVM c6608 IBL";
+
+hotmenu setConfig_c6608()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+
+ /* Main PLL: 100 MHz reference, 1GHz output */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+ /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
+ ibl.pllConfig[ibl_DDR_PLL].mult = 12;
+ ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
+
+ /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_NET_PLL].prediv = 1;
+ ibl.pllConfig[ibl_NET_PLL].mult = 21;
+ ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050;
+
+
+ ibl.ddrConfig.configDdr = 1;
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
+
+
+ ibl.sgmiiConfig[0].configure = 1;
+ ibl.sgmiiConfig[0].adviseAbility = 1;
+ ibl.sgmiiConfig[0].control = 1;
+ ibl.sgmiiConfig[0].txConfig = 0x108a1;
+ ibl.sgmiiConfig[0].rxConfig = 0x700621;
+ ibl.sgmiiConfig[0].auxConfig = 0x41;
+
+ ibl.sgmiiConfig[1].configure = 1;
+ ibl.sgmiiConfig[1].adviseAbility = 1;
+ ibl.sgmiiConfig[1].control = 1;
+ ibl.sgmiiConfig[1].txConfig = 0x108a1;
+ ibl.sgmiiConfig[1].rxConfig = 0x700621;
+ ibl.sgmiiConfig[1].auxConfig = 0x41;
+
+ ibl.mdioConfig.nMdioOps = 0;
+
+ ibl.spiConfig.addrWidth = 0;
+ ibl.spiConfig.nPins = 0;
+ ibl.spiConfig.mode = 0;
+ ibl.spiConfig.csel = 0;
+ ibl.spiConfig.c2tdelay = 0;
+ ibl.spiConfig.busFreqMHz = 0;
+
+ ibl.emifConfig[0].csSpace = 0;
+ ibl.emifConfig[0].busWidth = 0;
+ ibl.emifConfig[0].waitEnable = 0;
+
+ ibl.emifConfig[1].csSpace = 0;
+ ibl.emifConfig[1].busWidth = 0;
+ ibl.emifConfig[1].waitEnable = 0;
+
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = ibl_PORT_SWITCH_ALL;
+
+ ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
+ ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
+ ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,32,118);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,32,252);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,32,2);
+ SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Use the e-fuse value */
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 't';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = 'e';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = 's';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = 't';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '.';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'o';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'b';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
+ ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
+
+ ibl.chkSum = 0;
+
+}
diff --git a/src/util/spiConfig/makestg2 b/src/util/spiConfig/makestg2
--- /dev/null
@@ -0,0 +1,110 @@
+#**************************************************************************
+#* FILE PURPOSE: 2nd stage makefile for the spi parameter writer
+#**************************************************************************
+#* FILE NAME: makestg2
+#*
+#* DESCRIPTION: Builds the spi parameter writer for a specific target
+#*
+#**************************************************************************
+
+DEVICES= c6455 c6472 c6474 c6474l c6457 c661x
+
+ifndef IBL_ROOT
+ IBL_ROOT=../..
+endif
+
+ifeq ($(ENDIAN),big)
+ IEXT=be
+else
+ IEXT=le
+endif
+
+# Add SPI definitions
+SPI_CFG= $(addprefix -D,$(SPI_DEFS))
+
+# The PLL object files are device specific
+PLL_PATH= ../../hw/c64x/make
+ifeq ($(TARGET),c661x)
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc
+ PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
+ PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc
+else
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
+endif
+
+# Device specific helper utilities
+
+
+ECODIR= $(IBL_ROOT)/util/spiConfig
+ifeq ($(TARGET),c661x)
+ TFILES= ../../device/c64x/make/$(TARGET)util.$(IEXT).oc
+endif
+
+MODULES= hw
+CFG_MODULES= device
+
+CLEAN_MODULES=$(addprefix clean_,$(MODULES))
+CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES))
+
+
+CSRC= spiparam.c spiUtil.c
+
+CDEFS+= $(SPI_CFG)
+
+# enable debug info in the compile
+UTIL=yes
+
+include $(IBL_ROOT)/make/$(ARCH)/makeeco.mk
+
+C6X_C_DIR= $(IBL_ROOT)
+C6X_C_DIR+=;$(IBL_ROOT)/hw/spi
+C6X_C_DIR+=;$(IBL_ROOT)/hw/plls
+C6X_C_DIR+=;$(STDINC)
+C6X_C_DIR+=;$(IBL_ROOT)/cfg/$(TARGET)
+C6X_C_DIR+=;$(IBL_ROOT)/device/$(TARGET)
+C6X_C_DIR+=;$(IBL_ROOT)/arch/$(ARCH)
+C6X_C_DIR+=;$(IBL_ROOT)/util/spiWrite
+export C6X_C_DIR
+
+
+export ARCH
+export TARGET
+
+.PHONY: spiparam.cmd
+
+$(DEVICES): gen_cdefdep $(MODULES) $(CFG_MODULES) $(OBJS) spiparam.cmd
+ $(LD) -o spiparam_$(TARGET)_$(IEXT).out -m spiparam_$(TARGET)_$(IEXT).map spiparam.$(IEXT).oc ../spiWrite/spiutil.$(IEXT).oc ../../hw/c64x/make/spi.$(IEXT).oc ../../hw/c64x/make/spiutil.$(IEXT).oc $(PLL_OBJS) $(PSC_OBJS) $(TFILES) spiparam.cmd $(RTLIBS)
+
+$(MODULES):
+ @echo making $@
+ make -C $(IBL_ROOT)/$@/$(ARCH)/make $@
+
+$(CFG_MODULES):
+ @echo making $@
+ make -C $(IBL_ROOT)/$@/$(ARCH)/make CDEFS='$(MAINDEFS)' $@
+
+
+clean2: $(CLEAN_MODULES)
+ @rm -f $(OBJS)
+ @rm -f $(subst .c,.dc,$(CSRC))
+
+
+$(CLEAN_MODULES):
+ @echo cleaning $(subst clean_, ,$@)
+ make -C $(IBL_ROOT)/$(subst clean_,,$@)/$(ARCH)/make clean
+
+
+$(OBJS): cdefdep
+
+
+gen_cdefdep:
+ @echo Checking command line dependencies
+ @echo $(TARGET) $(ARCH) > cdefdep.tmp
+ @sh -c 'if diff -q cdefdep.tmp cdefdep ; then echo same ; else $(CP) cdefdep.tmp cdefdep ; fi '
+
+
+
+
+
+
+
diff --git a/src/util/spiConfig/spiparam.c b/src/util/spiConfig/spiparam.c
--- /dev/null
@@ -0,0 +1,190 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/*************************************************************************************
+ * FILE PURPOSE: Write the ibl configuration table to the spi eeprom
+ *************************************************************************************
+ * @file spiparam.c
+ *
+ * @brief
+ * Creates the ibl configuration table and writes to the spi
+ *
+ *************************************************************************************/
+
+#include "types.h"
+#include "ibl.h"
+#include "spi_api.h"
+#include "pllapi.h"
+#include "iblcfg.h"
+#include "target.h"
+#include "string.h"
+#include "spiWutil.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+ibl_t ibl;
+
+unsigned int configAddress = 0;
+unsigned int spiBlockSize = 256;
+
+#define MAX_SPI_BLOCK_SIZE 2048
+uint8 scratch[MAX_SPI_BLOCK_SIZE];
+
+spiConfig_t cfg = {
+
+ 0, /* port */
+ SPI_MODE, /* mode */
+ SPI_ADDR_WIDTH, /* address width */
+ SPI_NPIN, /* number of pins */
+ SPI_CSEL, /* csel */
+ SPI_CLKDIV, /* clock divider */
+ SPI_C2TDEL /* ct2delay */
+
+};
+
+/**
+ * @brief
+ * Ones complement addition
+ */
+inline uint16 onesComplementAdd (uint16 value1, uint16 value2)
+{
+ uint32 result;
+
+ result = (uint32)value1 + (uint32)value2;
+
+ result = (result >> 16) + (result & 0xFFFF); /* add in carry */
+ result += (result >> 16); /* maybe one more */
+ return ((uint16)result);
+}
+
+
+/**
+ * @brief
+ * Ones complement checksum computation
+ */
+uint16 onesComplementChksum (uint16 * restrict p_data, uint16 len)
+{
+ uint16 chksum = 0;
+
+ while (len > 0)
+ {
+ chksum = onesComplementAdd(chksum, *p_data);
+ p_data++;
+ len--;
+ }
+ return (chksum);
+}
+
+
+void main (void)
+{
+ int result;
+ uint16 chk;
+ int nblocks;
+ uint32 addr;
+ uint32 *iblUi32;
+
+ volatile Int32 i;
+
+ if (spiBlockSize > MAX_SPI_BLOCK_SIZE) {
+ printf ("Error: spi block size (%d) greater then this program can handle (%d).\n", spiBlockSize, MAX_SPI_BLOCK_SIZE);
+ printf (" Change the definition of MAX_SPI_BLOCK_SIZE and recompile\n");
+ return;
+ }
+
+ if (configAddress == 0) {
+ printf ("Error: The global variable config address must be setup prior to running this program\n");
+ printf (" This is the address in the I2C eeprom where the parameters live. On configurations\n");
+ printf (" which support both big and little endian it is possible to configure the IBL to\n");
+ printf (" usage a different configuration table for each endian, so this program must be run\n");
+ printf (" twice. The value 0 is invalid for configAddress\n");
+ return;
+ }
+
+ printf ("Run the GEL for for the device to be configured, press return to program the I2C\n");
+ getchar ();
+
+ /* Program the main system PLL */
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv, /* Pre-divider */
+ ibl.pllConfig[ibl_MAIN_PLL].mult, /* Multiplier */
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv); /* Post-divider */
+
+
+ result = hwSpiConfig (&cfg);
+ if (result != 0) {
+ printf ("hwSpiConfig returned error %d\n", result);
+ return;
+ }
+
+
+ /* Compute the checksum over the ibl configuration structure */
+ ibl.chkSum = 0;
+ chk = onesComplementChksum ((uint16 *)&ibl, sizeof(ibl_t)/sizeof(uint16));
+ if (ibl.chkSum != 0xffff)
+ ibl.chkSum = ~chk;
+
+
+
+ /* Write the configuration table out one block at a time */
+ nblocks = (sizeof(ibl_t) + spiBlockSize - 1) / spiBlockSize;
+ iblUi32 = (uint32 *)&ibl;
+
+ for (i = 0, addr = configAddress; i < nblocks; i++, addr += spiBlockSize) {
+
+ result = writeBlock (&cfg, addr, &iblUi32[(i * spiBlockSize) >> 2], spiBlockSize, scratch);
+ if (result != 0) {
+ printf ("writeBlock returned error code %d, exiting\n", result);
+ return;
+ }
+ }
+
+
+ printf ("SPI table write complete\n");
+
+}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/util/spiConfig/spiparam.cmd b/src/util/spiConfig/spiparam.cmd
--- /dev/null
@@ -0,0 +1,38 @@
+/*************************************************************************
+ * @file i2cparam_c6472.cmd
+ *
+ * @brief Places the i2c parameter writer program into memory
+ *
+ *************************************************************************/
+
+/* Object files included in linker invokation */
+
+-c
+-a
+-stack 0x400
+
+MEMORY
+{
+ STACK : origin = 0x810000 length = 0x0400
+ TEXT : origin = 0x810400 length = 0x9000
+ DATA : origin = 0x819400 length = 0x2000
+ SYSMEM : origin = 0x829400 length = 0x0800
+}
+
+SECTIONS
+{
+ .stack > STACK
+
+ .text > TEXT
+ .const > TEXT
+ .switch > TEXT
+ .cinit > TEXT
+
+ .far > DATA
+ .bss > DATA
+ .data > DATA
+
+ .sysmem > SYSMEM
+
+}
+
\ No newline at end of file
diff --git a/src/util/spiWrite/Makefile b/src/util/spiWrite/Makefile
--- /dev/null
@@ -0,0 +1,65 @@
+#*
+#*
+#* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#*
+#*
+#* Redistribution and use in source and binary forms, with or without
+#* modification, are permitted provided that the following conditions
+#* are met:
+#*
+#* Redistributions of source code must retain the above copyright
+#* notice, this list of conditions and the following disclaimer.
+#*
+#* Redistributions in binary form must reproduce the above copyright
+#* notice, this list of conditions and the following disclaimer in the
+#* documentation and/or other materials provided with the
+#* distribution.
+#*
+#* Neither the name of Texas Instruments Incorporated nor the names of
+#* its contributors may be used to endorse or promote products derived
+#* from this software without specific prior written permission.
+#*
+#* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#*
+
+
+#***************************************************************
+#* FILE PURPOSE: Top level make file for the SPI writer
+#***************************************************************
+#* FILE NAME: Makefile
+#*
+#* DESCRIPTION: builds the spi eeprom writer
+#*
+#***************************************************************
+
+DEVICES= c6455 c6472 c6474 c6474l c6457 c661x
+
+all:
+ @echo must specify a target [ $(DEVICE) ]
+
+ifndef ENDIAN
+ ENDIAN= little
+endif
+
+export ENDIAN
+
+$(DEVICES):
+ make -f makestg2 ARCH=c64x TARGET=$@ $@
+
+clean:
+ make -f makestg2 clean2 ARCH=c64x
+
+
+
+
+
diff --git a/src/util/spiWrite/makestg2 b/src/util/spiWrite/makestg2
--- /dev/null
@@ -0,0 +1,103 @@
+#*********************************************************************************
+#* FILE PURPOSE: Build the SPI EEPROM writer
+#*********************************************************************************
+#* FILE NAME: makestg2
+#*
+#* DESCRIPTION: Builds the spi writer
+#*
+#*********************************************************************************
+
+
+DEVICES= c6455 c6472 c6474 c6474l c6457 c661x
+
+ifndef IBL_ROOT
+ IBL_ROOT=../..
+endif
+
+ifeq ($(ENDIAN),big)
+ IEXT=be
+else
+ IEXT=le
+endif
+
+# Add SPI definitions
+SPI_CFG= $(addprefix -D,$(SPI_DEFS))
+
+# The PLL object files are device specific
+PLL_PATH= ../../hw/c64x/make
+ifeq ($(TARGET),c661x)
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc
+ PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
+ PSC_OBJS+= ../../hw/c64x/make/psc.$(IEXT).oc
+else
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
+endif
+
+
+ifeq ($(TARGET),c661x)
+ TFILES= ../../device/c64x/make/$(TARGET)util.$(IEXT).oc
+endif
+
+
+
+ECODIR= $(IBL_ROOT)/util/spiWrite
+
+MODULES= hw
+CFG_MODULES= device
+
+CLEAN_MODULES=$(addprefix clean_,$(MODULES))
+CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES))
+
+CSRC= spiWrite.c spiUtil.c
+
+CDEFS+= $(SPI_CFG)
+
+
+# enable debug info in the compile
+UTIL=yes
+
+include $(IBL_ROOT)/make/$(ARCH)/makeeco.mk
+
+C6X_C_DIR= $(IBL_ROOT)/hw/spi
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/plls
+C6X_C_DIR+= ;$(IBL_ROOT)/cfg/$(TARGET)
+C6X_C_DIR+= ;$(IBL_ROOT)/device/$(TARGET)
+C6X_C_DIR+= ;$(IBL_ROOT)/arch/$(ARCH)
+C6X_C_DIR+= ;$(STDINC)
+export C6X_C_DIR
+
+export ARCH
+export TARGET
+
+
+
+
+$(DEVICES): gen_cdefdep $(MODULES) $(CFG_MODULES) $(OBJS) spiWrite.cmd
+ $(LD) -o spiWrite_$(IEXT).out -m spiWrite_$(IEXT).map spiWrite.$(IEXT).oc spiUtil.$(IEXT).oc ../../hw/c64x/make/spi.$(IEXT).oc ../../hw/c64x/make/spiutil.$(IEXT).oc $(PLL_OBJS) $(PSC_OBJS) $(TFILES) spiWrite.cmd $(RTLIBS)
+
+
+$(MODULES):
+ @echo making $@
+ make -C $(IBL_ROOT)/$@/$(ARCH)/make $@
+
+$(CFG_MODULES):
+ @echo making $@
+ make -C $(IBL_ROOT)/$@/$(ARCH)/make CDEFS='$(MAINDEFS)' $@
+
+
+clean2: $(CLEAN_MODULES)
+ @rm -f $(OBJS)
+ @rm -f $(subst .c,.dc,$(CSRC))
+
+$(CLEAN_MODULES):
+ @echo cleaning $(subst clean_, ,$@)
+ make -C $(IBL_ROOT)/$(subst clean,,$@)/$(ARCH)/make clean
+
+$(OBJS): cdefdep
+
+
+gen_cdefdep:
+ @echo Checking command line dependencies
+ @echo $(ARCH) $(TARGET) $(SPI_DEFS) > cdefdep.tmp
+ @sh -c 'if diff -q cdefdep.tmp cdefdep ; then echo same ; else $(CP) cdefdep.tmp cdefdep ; fi '
+
diff --git a/src/util/spiWrite/spiUtil.c b/src/util/spiWrite/spiUtil.c
--- /dev/null
@@ -0,0 +1,220 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @file spiUtil.c
+ *
+ * @brief
+ * I2C access functions
+ */
+#include "types.h"
+#include "spi_api.h"
+#include "target.h"
+#include "spi_loc.h"
+#include "spiWutil.h"
+
+
+/**
+ * @brief Wait until the Write In Progress bit is clear
+ */
+
+void waitWip (spiConfig_t *cfg)
+{
+ uint8 cmdBuf[4];
+ uint8 rBuf[4];
+
+ /* Loop until the status register write in progress is clear */
+ hwSpiEnableXfer (cfg->port);
+ do {
+
+ cmdBuf[0] = SPI_COMMAND_READ_STATUS;
+
+ hw_spi_xfer (1, cmdBuf, NULL, cfg, FALSE);
+ hw_spi_xfer (1, NULL, rBuf, cfg, TRUE);
+
+ } while (rBuf[0] & 0x1);
+
+ hwSpiDisableXfer (cfg->port);
+
+}
+
+
+
+/**
+ * @brief Erase a sector, wait for completion
+ */
+int eraseSector (spiConfig_t *cfg, unsigned address)
+{
+ int ret;
+ uint8 cmdBuf[4];
+ UINT16 n;
+
+ hwSpiEnableXfer (cfg->port);
+
+ /* Enable write */
+ cmdBuf[0] = SPI_COMMAND_WRITE_ENABLE;
+ ret = hw_spi_xfer (1, cmdBuf, NULL, cfg, TRUE);
+ if (ret != 0)
+ return (ret);
+
+ /* Send the erase */
+ cmdBuf[0] = SPI_COMMAND_ERASE_SECTOR;
+
+ if (cfg->addrWidth == 24) {
+ cmdBuf[1] = (address >> 16) & 0xff;
+ cmdBuf[2] = (address >> 8) & 0xff;
+ cmdBuf[3] = (address >> 0) & 0xff;
+ n = 4;
+
+ } else {
+ cmdBuf[1] = (address >> 8) & 0xff;
+ cmdBuf[2] = (address >> 0) & 0xff;
+ n = 3;
+ }
+
+
+ ret = hw_spi_xfer (n, cmdBuf, NULL, cfg, TRUE);
+
+ waitWip (cfg);
+
+ return (0);
+
+}
+
+
+/**
+ * @brief Write data to the SPI
+ */
+
+int writeBlock (spiConfig_t *cfg, unsigned int address, uint32 *data, int blockSize, uint8 *scratch)
+{
+ uint8 cmdBuf[4];
+ UINT16 n;
+ int i, j;
+ int ret;
+
+ /* Convert the data to a byte stream */
+ for (i = j = 0; j < blockSize; i++, j+=4) {
+ scratch[j+0] = (data[i] >> 24) & 0xff;
+ scratch[j+1] = (data[i] >> 16) & 0xff;
+ scratch[j+2] = (data[i] >> 8) & 0xff;
+ scratch[j+3] = (data[i] >> 0) & 0xff;
+ }
+
+
+ /* Enable write */
+ hwSpiEnableXfer (cfg->port);
+ cmdBuf[0] = SPI_COMMAND_WRITE_ENABLE;
+ ret = hw_spi_xfer (1, cmdBuf, NULL, cfg, TRUE);
+ if (ret != 0)
+ return (ret);
+
+ /* Send the write command */
+ cmdBuf[0] = SPI_COMMAND_WRITE;
+
+ if (cfg->addrWidth == 24) {
+ cmdBuf[1] = (address >> 16) & 0xff;
+ cmdBuf[2] = (address >> 8) & 0xff;
+ cmdBuf[3] = (address >> 0) & 0xff;
+ n = 4;
+
+ } else {
+ cmdBuf[1] = (address >> 8) & 0xff;
+ cmdBuf[2] = (address >> 0) & 0xff;
+ n = 3;
+ }
+
+ /* Send the command and address */
+ ret = hw_spi_xfer (n, cmdBuf, NULL, cfg, FALSE);
+ if (ret != 0)
+ return (ret);
+
+ /* Send the data */
+ ret = hw_spi_xfer (blockSize, scratch, NULL, cfg, TRUE);
+ if (ret != 0)
+ return (ret);
+
+ waitWip (cfg);
+
+ return (0);
+
+}
+
+
+/*
+ * @brief Read a block of data
+ */
+int readBlock (spiConfig_t *cfg, unsigned int address, uint8 *data, int blockSize)
+{
+ uint8 cmdBuf[4];
+ UINT16 n;
+ int ret;
+
+ /* Send the read command */
+ cmdBuf[0] = SPI_COMMAND_READ;
+
+ if (cfg->addrWidth == 24) {
+ cmdBuf[1] = (address >> 16) & 0xff;
+ cmdBuf[2] = (address >> 8) & 0xff;
+ cmdBuf[3] = (address >> 0) & 0xff;
+ n = 4;
+
+ } else {
+ cmdBuf[1] = (address >> 8) & 0xff;
+ cmdBuf[2] = (address >> 0) & 0xff;
+ n = 3;
+ }
+
+
+
+ /* Send the command and address */
+ hwSpiEnableXfer (cfg->port);
+ ret = hw_spi_xfer (n, cmdBuf, NULL, cfg, FALSE);
+ if (ret != 0)
+ return (ret);
+
+ /* Send the data */
+ ret = hw_spi_xfer (blockSize, NULL, data, cfg, TRUE);
+ if (ret != 0)
+ return (ret);
+
+ hwSpiDisableXfer (cfg->port);
+
+ return (0);
+
+}
+
+
+
diff --git a/src/util/spiWrite/spiWrite.c b/src/util/spiWrite/spiWrite.c
--- /dev/null
@@ -0,0 +1,210 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @file spiWrite.c
+ *
+ * @brief
+ * Write to an SPI eeprom
+ */
+
+#include "types.h"
+#include "spi_api.h"
+#include "target.h"
+#include "pllapi.h"
+#include <stdio.h>
+#include <string.h>
+
+#pragma DATA_SECTION(txData, ".tx_data")
+#pragma DATA_SECTION(rxData, ".rx_data")
+
+#define MAX_DATA_SIZE 0x40000 /* 256 kb */
+uint32 txData[MAX_DATA_SIZE >> 2];
+uint32 rxData[MAX_DATA_SIZE >> 2];
+
+#define MAX_BLOCK_SIZE 2048
+uint8 scratchBlock[MAX_BLOCK_SIZE];
+
+unsigned int nbytes = MAX_DATA_SIZE;
+unsigned int startAddress = 0;
+
+/* Run time configuration */
+unsigned int deviceFreqMhz = 1000;
+unsigned int prediv = 1;
+unsigned int mult = 20;
+unsigned int postdiv = 2;
+
+unsigned int spiBlockSize = 256;
+unsigned int spiSectorSize = 4096; /* Erase size */
+
+spiConfig_t cfg = {
+
+ 0, /* port */
+ SPI_MODE, /* mode */
+ SPI_ADDR_WIDTH, /* address width */
+ SPI_NPIN, /* number of pins */
+ SPI_CSEL, /* csel */
+ SPI_CLKDIV, /* clock divider */
+ SPI_C2TDEL /* ct2delay */
+
+};
+
+
+
+int main (void)
+{
+ int result;
+ int firstSector;
+ int lastSector;
+ int nblocks;
+ int i, j, k;
+
+ unsigned int addr;
+
+ /* This writer requires that the start address be block aligned */
+ if ((startAddress % spiBlockSize) != 0) {
+ printf ("spiWriter requires that the start address be block aligned, exiting\n");
+ return (-1);
+ }
+
+ /* Check that the block size is within range */
+ if (spiBlockSize > MAX_BLOCK_SIZE) {
+ printf ("The block size selected (%d) is greater then the max size of %d.\n", spiBlockSize, MAX_BLOCK_SIZE);
+ printf ("Increase the value of MAX_BLOCK_SIZE and recompile the program\n");
+ return (-1);
+ }
+
+ /* Power up the SPI */
+ #ifdef TARGET_PWR_SPI
+ devicePowerPeriph (TARGET_PWR_SPI);
+ #endif
+
+
+ /* Program the main system PLL */
+ hwPllSetPll (0, /* Main PLL */
+ prediv, /* Pre-divider */
+ mult, /* Multiplier */
+ postdiv); /* Post-divider */
+
+
+ result = hwSpiConfig (&cfg);
+ if (result != 0) {
+ printf ("hwSpiConfig returned error %d\n", result);
+ return (-1);
+ }
+
+ /* Erase all sectors that will be used */
+ firstSector = startAddress / spiSectorSize;
+ lastSector = (startAddress + nbytes + spiSectorSize - 1) / spiSectorSize;
+
+ printf ("Erasing sector: ");
+ for (i = firstSector; i <= lastSector; i++) {
+ printf ("%d ", i);
+ eraseSector (&cfg, i * spiSectorSize);
+ }
+
+ printf ("done\n");
+
+
+ /* Program all the data */
+ nblocks = (nbytes + spiBlockSize - 1) / spiBlockSize;
+
+ printf ("Writing blocks ");
+ for (i = 0, addr = startAddress; i < nblocks; i++, addr += spiBlockSize) {
+
+ result = writeBlock (&cfg, addr, &txData[(i * spiBlockSize) >> 2], spiBlockSize, scratchBlock);
+ if (result != 0) {
+ printf ("\nwriteBlock returned error code %d, exiting\n", result);
+ return (-1);
+ }
+
+ printf (".");
+ }
+
+ printf ("\n");
+
+
+ /* Read the data as bytes. Translate it to words */
+ printf ("Reading blocks ");
+ for (i = j = 0, addr = startAddress; i < nblocks; i++, addr += spiBlockSize) {
+
+ result = readBlock (&cfg, addr, scratchBlock, spiBlockSize);
+
+ if (result != 0) {
+ printf ("\nreadBlock returned error code %d, exiting\n", result);
+ return (-1);
+ }
+
+ for (k = 0; k < spiBlockSize; k += 4)
+ rxData[j++] = (scratchBlock[k+0] << 24) | (scratchBlock[k+1] << 16) | (scratchBlock[k+2] << 8) | scratchBlock[k+3];
+
+ printf (".");
+ }
+
+ printf ("\n");
+
+ /* Compare the results */
+ printf ("Checking the read back\n");
+
+ for (i = j = 0; i < nbytes >> 2; i++) {
+
+ if (txData[i] != rxData[i]) {
+
+ j += 1;
+ printf ("failure at word %d: Expected 0x%04x, found 0x%04x\n", i, txData[i], rxData[i]);
+
+ }
+
+ if (j >= 5) {
+ printf ("Too many errors, quitting\n");
+ break;
+ }
+ }
+
+ if (j == 0)
+ printf ("Read back verified\n");
+
+
+ return (0);
+
+}
+
+
+
+
+
+
+
+
diff --git a/src/util/spiWrite/spiWrite.cmd b/src/util/spiWrite/spiWrite.cmd
--- /dev/null
@@ -0,0 +1,35 @@
+
+
+/* Object file list provided in linker invokation */
+
+-c
+-a
+-stack 0x400
+
+MEMORY
+{
+ L2 : origin = 0x800000 length = 0x10000
+
+ TX : origin = 0x0c000000 length = 0x80000
+ RX : origin = 0x0c080000 length = 0x80000
+
+}
+
+SECTIONS
+{
+ .text > L2
+ .heap > L2
+ .stack > L2
+ .cinit > L2
+ .const > L2
+ .far > L2
+ .sysmem > L2
+ .cio > L2
+ .switch > L2
+
+ .tx_data > TX
+ .rx_data > RX
+
+}
+
+
diff --git a/src/util/spiWrite/spiWutil.h b/src/util/spiWrite/spiWutil.h
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @file spiWutil.h
+ */
+#ifndef _SPI_W_UTIL_H
+#define _SPI_W_UTIL_H
+
+#include "spi_api.h"
+
+int eraseSector (spiConfig_t *cfg, unsigned address);
+int writeBlock (spiConfig_t *cfg, unsigned int address, uint32 *data, int blockSize, uint8 *scratch);
+int readBlock (spiConfig_t *cfg, unsigned int address, uint8 *data, int blockSize);
+
+
+
+#endif
+
+