c66x IBL Config: Upadte DDR PLL init values
authorSandeep Paulraj <s-paulraj@ti.com>
Tue, 8 Nov 2011 19:51:58 +0000 (14:51 -0500)
committerSandeep Paulraj <s-paulraj@ti.com>
Tue, 8 Nov 2011 19:51:58 +0000 (14:51 -0500)
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/util/iblConfig/src/device.c

index c02df1000d8becf5a80a6ed2c4dd25c1ca613466..6c6c1819faa2d2ea5e64483fecb1a89ec87a9785 100644 (file)
@@ -722,12 +722,12 @@ ibl_t c6678_ibl_config(void)
        ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
 
-       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
+       /* DDR PLL: */
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
-       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
-       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;
 
     /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
@@ -939,12 +939,12 @@ ibl_t c6670_ibl_config(void)
        ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
-       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
+       /* DDR PLL */
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
-       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 20;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
-       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 1333;
 
     /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
        ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
@@ -1097,15 +1097,15 @@ ibl_t c6670_ibl_config(void)
        ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
        ibl.bootModes[2].port     = ibl_PORT_SWITCH_ALL;
 
-       ibl.bootModes[2].u.ethBoot.doBootp          = TRUE;
+       ibl.bootModes[2].u.ethBoot.doBootp          = FALSE;
        ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
        ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
        ibl.bootModes[2].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;
 
 
-    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr,    192,168,1,3);
-    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp,  192,168,1,2);
-    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr,    158,218,100,113);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp,  158,218,100,251);
+    SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 158,218,100,1);
     SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask,   255,255,255,0);
 
     /* Use the e-fuse value */