Clearing DDR3 memory in IBL (workaround for failing to load NAND image) DEV.MAD_UTILS.IBL.01.00.00.13
authorIvan Pang <i-pang@ti.com>
Thu, 8 Mar 2012 17:00:50 +0000 (12:00 -0500)
committerIvan Pang <i-pang@ti.com>
Thu, 8 Mar 2012 17:00:50 +0000 (12:00 -0500)
src/device/c66x/c66x.c
src/device/c66x/c66xutil.c
src/device/c66x/target.h

index ba72d9045a489fc06cc7647e70f5c969510da839..0fcdd99e7628988472d1e4754a262565eab150e7 100755 (executable)
@@ -195,6 +195,8 @@ void deviceDdrConfig (void)
     else
     {
         uart_write_string("IBL: PLL and DDR Initialization Complete",0);
+        /* Clear the 16MB DDR3 memory - Workaround - should be removed after Linux fixes the issue */
+        ddr3_memory_zero(16);
     }
     uart_write_string(ddr_result_code_str,0);
 #endif
index 29cf7521a7d651bccbe47bffde6e5be81520da7c..8b61a5d5e050485ea1c7951c3399f9cae80dee63 100644 (file)
@@ -174,5 +174,15 @@ UINT32 ddr3_memory_test (void)
        return 0;
 }
 
+void ddr3_memory_zero(UINT32 size_mb )
+{
+        UINT32 index;
+
+       /* clear memory */
+       for (index = DDR3_TEST_START_ADDRESS; index < (DDR3_TEST_START_ADDRESS + (size_mb *1024*1024)); index += 4) {
+               *(VUint32 *) index = (UINT32)0;
+       }
+}
+
 #endif
 
index ed3018dc7e2ba15ff244275952f9ce50eb9d7d51..a89b70c20c2ba71c177f4be6e2db620ad5fa0ad2 100644 (file)
@@ -415,6 +415,6 @@ Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
 #define PLL_REINIT_WORKAROUND
 
 UINT32 ddr3_memory_test();
-
+void ddr3_memory_zero(UINT32 size_mb );
 #endif /* _TARGET_H */